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magnachip semiconductor ltd. 8-bit single-chip microcontrollers mc80f0208/16/24 mc80c0208/16/24 user?s manual (ver. 0.2) preliminary
version 0.2 published by mcu application team ? 2005 magnachip semiconductor inc. all righ t reserved. additional information of this ma nual may be served by magnachip semiconductor offices in korea or distributors and representat ives. magnachip semiconductor reserves the right to make changes to any informat ion here in at any time without notice. the information, diagrams and ot her data in this manual are corre ct and reliable; however, magna chip semiconductor is in no way re- sponsible for any violations of pate nts or other rights of the third part y generated by the use of this manual. revision history version 0.2 (mar. 2005) this book
mc80f0208/16/24 mar. 2005 ver 0.2 1. overview ................................................................................................................... ................................. 1 description ................................................................................................................... ................................. 1 features ...................................................................................................................... .................................. 1 ordering information ............................................................... ................................................................ 2 development tools ............................................................................................................. .......................... 3 2. block diagram .............................................................................................................. .......................... 4 3. pin assignment ............................................................................................................. ........................... 5 4. package diagram ............................................................................................................ ....................... 6 5. pin function ............................................................................................................... ............................... 7 pin description ............................................................................................................... ............................... 8 6. port structures ............................................................................................................ ...................... 10 7. electrical characteristics ................................................................................................. .......... 13 absolute maximum ratings ............................... ....................................................................... .................. 13 recommended operating conditions .............................................................................................. ........... 13 a/d converter characteristics ................................................................................................. ................... 13 dc electrical characteristics ................................................................................................. ..................... 14 ac characteristics ............................................................................................................ .......................... 15 serial interface timing characteristics ....................................................................................... ................ 16 typical characteristic curves ................................................................................................. .................... 17 8. memory organization ........................................................................................................ ................ 19 registers ..................................................................................................................... ................................ 19 program memory ................................................................................................................ ........................ 21 data memory ................................................................................................................... ........................... 25 addressing mode ............................................................................................................... ......................... 31 9. i/o ports .................................................................................................................. ................................. 35 10. clock generator ........................................................................................................... ................... 39 11. basic interval timer ...................................................................................................... ................... 40 12. watchdog timer ............................................................................................................ ..................... 42 13. watch timer ............................................................................................................... ........................... 45 14. timer/event counter ........... ................. ................ ................ ................ ................ ........... ................. 46 8-bit timer / counter mode .................................................................................................... ..................... 50 16-bit timer / counter mode ................................................................................................... .................... 56 8-bit compare output (16-bit) ................................................................................................. .................... 57 8-bit capture mode ............................................................................................................ ......................... 58 16-bit capture mode ........................................................................................................... ........................ 62 pwm mode ...................................................................................................................... ........................... 65 15. analog to digital converter ............................................................................................... ........ 68 16. serial input/output (sio) ................................................................................................. ................ 71 transmission/receiving timing .. ............................................................................................... ................. 72 the method of serial i/o ...................................................................................................... ....................... 74 the method to test correct tran smission ....................................................................................... ........... 74 17. universal asynchronous receiver/transmitter (uart) ................................................... 75 uart serial interface functions ............................................................................................... ................. 75
mc80f0208/16/24 mar. 2005 ver 0.2 serial interface configuration ................................................................................................ ..................... 77 communication operation ....................................................................................................... .................... 80 relationship between main clock and baud rate ................................................................................. ....... 82 18. buzzer function ........................................................................................................... ...................... 83 19. interrupts ................................................................................................................ ............................ 85 interrupt sequence ............................................................................................................ ......................... 87 brk interrupt ................................................................................................................. ............................. 89 shared interrupt vector ......... .............................................................................................. ........................ 89 multi interrupt ............................................................................................................... ............................... 90 external interrup t ............................................................................................................ ............................ 91 20. operation mode ............................................................................................................ ...................... 93 operation mode switching ...................................................................................................... .................... 93 21. power saving operation .................................................................................................... ............ 94 sleep mode .................................................................................................................... ............................. 94 stop mode ..................................................................................................................... .............................. 95 stop mode at internal rc-oscillat ed watchdog timer mode ..................................................................... 98 minimizing current consumption ................................................................................................ .............. 100 22. oscillator circuit ........................................................................................................ .................. 102 23. reset ..................................................................................................................... ................................ 103 24. power fail processor ...................................................................................................... ............. 104 25. flash programming ......................................................................................................... ............... 106 device configuration area ..................................................................................................... ................... 106 26. emulator eva. board setting ............................................................................................. ................. 107 27. in-system programming (isp) ................ ................ ................ ................ ................ ............... ........ 110 getting started / installation ................................................................................................ ...................... 110 basic isp s/w information ..................................................................................................... ................... 110 hardware conditions to enter the isp mode ........................... .......................................................... ....... 111 reference isp circuit diagram ................................................................................................. ................ 113 a. instruction ................................................................................................................ ............................... i terminology list .............................................................................................................. ................................i instruction map ............................................................................................................... ...............................ii instruction set ............................................................................................................... ................................ iii b. mask order sheet ........................................................................................................... ..................... ix
preliminary mc80f0208/16/24 mar. 2005 ver 0.2 1 mc80f0208/16/24 mc80c0208/16/24 cmos single-chip 8-bit microcontroller with 10-bit a/d converter and uart 1. overview 1.1 description the mc80f0208/16/24 is advanced cmos 8-bi t microcontroller with 8k/16k /24k bytes of flash(rom). this is a powerful microcon- troller which provides a highly flexible a nd cost effective solution to many embedded control applic ations. this provides the f ollowing standard features : 8k/16k/24k bytes of fl ash, 1k bytes of ram, 8/16- bit timer/counter, wa tchdog timer, watch t imer, 10-bit a/d con- verter, 8-bit serial input/output, uart, buz zer driving port, 10-bit pwm output and on-ch ip oscillator and cl ock circuitry. it also has 8 high current i/o pins with typi cal 20ma. in addition, the mc80f 0208/16/24 supports power saving m odes to reduce power consumpti on. 1.2 features ? 8k/16k/24k bytes on-chip rom ? flash mermory - endurance : 100 cycles - data retention : 10 years ? 1024 bytes on-chip data ram (included stack memory) ? minimum instruction execution time - 333ns at 12mhz (nop instruction) ? 36 i/o ports ? one 8-bit basic interval timer ? four 8-bit and one 16-bit timer/event counter (or three 16-bit timer/event counter) ? one watchdog timer ? one watch timer ? one 10-bit pwm ? 8 channel 10-bit a/d converter ? three 8-bit serial communication interface - one serial i/o and two uart ? one buzzer driving port - 488hz ~ 250khz@4mhz ? four external interrupt input ports ? fifteen interrupt sources - basic interval timer(1) - external input(4) - timer/event counter(5) - adc(1) - serial interface(1), uart(2) - wdt and watch timer(1) ? built in noise immunity circuit - noise filter - 3-level power fail detector [3.0v, 2.7v, 2.4v] ? power down mode - stop, sleep mode ? operating voltage range - 2.7v ~ 5.5v (@ 8mhz) - 4.5v ~ 5.5v (@ 12mhz) device name flash(rom) size ram adc pwm i/o port package flash mask rom mc80f0208q mc80c0208q 8kbyte 1024 byte 8 channel 1 channel 36 port 44mqfp mc80f0208k mc80c0208k 42sdip mc80f0216q mc80c0216q 16kbyte 1024 byte 8 channel 1 channel 36 port 44mqfp mc80f0216k mc80c0216k 42sdip mc80f0224q MC80C0224Q 24kbyte 1024 byte 8 channel 1 channel 36 port 44mqfp mc80f0224k mc80c0224k 42sdip
mc80f0208/16/24 preliminary 2 mar. 2005 ver 0.2 ? operating frequency range - 0.4 ~ 12mhz ? 44mqfp, 42sdip type ? operating temperature : -40c ~ 85c ? oscillator type - crystal, ceramic reso nator, external clock 1.3 ordering information table 1-1 ordering information of mc80f0208/16/24 & mc80c0208/16/24 rom type device name rom size ram size package mask version mc80c0208q mc80c0208k 8k bytes 8k bytes 1024 bytes 44mqfp 42sdip mc80c0216q mc80c0216k 16k bytes 16k bytes 1024 bytes 44mqfp 42sdip MC80C0224Q mc80c0224k 24k bytes 24k bytes 1024 bytes 44mqfp 42sdip flash version mc80f0208q mc80f0208k 8k bytes flash 8k bytes flash 1024 bytes 44mqfp 42sdip mc80f0216q mc80f0216k 16k bytes flash 16k bytes flash 1024 bytes 44mqfp 42sdip mc80f0224q mc80f0224k 24k bytes flash 24k bytes flash 1024 bytes 44mqfp 42sdip
preliminary mc80f0208/16/24 mar. 2005 ver 0.2 3 1.4 development tools the mc80f0208/16/24 is supported by a full-featured macro as- sembler, an in-circu it emulator choice-dr. tm and otp pro- grammers. there are two different type of programmers such as single type and gang type. for mode detail, macro assembler op- erates under the ms-windows 95 and upversioned windows os. please contact sa les part of magna chip semiconductor. software - ms-windows based assembler - ms-windows based debugger - mc800 c compiler hardware (emulator) - choice-dr. - choice-dr. eva80c0x b/d flash writer - choice - sigma i/ii(single writer) - pgm plus i/ii/iii(single writer) - standalone gang4 i/ii(gang writer) pgmplus iii ( single writer ) choice-dr. (emulator) standalone gang4 ii ( gang writer )
mc80f0208/16/24 preliminary 4 mar. 2005 ver 0.2 2. block diagram interrupt controller data memory 10-bit adc 8-bit counter timer/ program memory data table pc watch/ timer instruction r1 r4 psw system controller timing generator system clock controller clock generator reset x in x out r10/int0 r11/int1 r40 power supply 8-bit serial r41 r42/sck r43/si r44/so r45/aclk0 r46/rxd0 r47/txd0 interface buzzer driver r6 r60/an0 r61/an1 r62/an2 r63/an3 r64/an4 r65/an5 r66/an6 r67/an7 (1024 bytes) 10-bit av dd adc power supply stack pointer r0 r00~r07 r12/int2 r13/buzo pwm a x y sio/uart0 r15/ec0 r50/int3 r51/ec1 r54/pwm3o/t3o r5 watchdog 8-bit basic timer interval v dd v ss decoder r3 r30 8-bit serial r31/aclk1 r32/rxd1 r33/txd1 interface uart1 alu
preliminary mc80f0208/16/24 mar. 2005 ver 0.2 5 3. pin assignment v dd an4 / r64 an5 / r65 an6 / r66 an7 / r67 r00 r01 r02 r03 r04 r05 r06 r07 int0 / r10 int1 / r11 int2 / r12 buzo / r13 ec0 / r15 reset x in x out r63 / an3 r62 / an2 r61 / an1 r60 / an0 v ss r54 / pwm3o / t3o r51 / ec1 r50 / int3 r47 / txd0 r46 / rxd0 r45 / aclk0 r44 / so r43 / si r42 / sck r41 r40 r33 / txd1 r32 / rxd1 r31 / aclk1 r30 42sdip 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 mc80f0208k/16k/24k (top view) av dd nc r33 / txd1 r32 / rxd1 r31 / aclk1 r30 v ss x out x in reset r15 / ec0 r13 / buzo av dd r51 / ec1 r50 / int3 r47 / txd0 r46 / rxd0 r45 / aclk0 r44 / so r43 / si r42 / sck r41 r40 r00 r01 r02 r03 r04 r05 r06 r07 int0 / r10 int1 / r11 int2 / r12 1 2 3 4 5 6 7 8 9 10 11 an1 / r61 an2 / r62 an3 / r63 an4 / r64 an5 / r65 an6 / r66 an7 / r67 v dd 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 35 36 37 38 39 40 41 42 43 mc80f0208q/16q/24q 44mqfp (top view) t3o / pwm3o / r54 34 an0 / r60 nc 44
mc80f0208/16/24 preliminary 6 mar. 2005 ver 0.2 4. package diagram unit: inch 1.470 1.450 0.020 0.016 0.045 0.035 0.070 bsc 0.140 0.120 min. 0.015 0.550 0.530 0.600 bsc 0-15 42sdip 0 . 0 1 2 0 . 0 0 8 0.190 max. 10.10 9.90 13.45 12.95 13.45 12.95 10.10 9.90 2.35 max. 0.45 0.30 0.80 bsc see detail ?a? 1.03 0.73 0-7 0.25 0.10 0.23 0.13 1.60 bsc detail ?a? unit: mm 44mqfp 2.10 1.95
preliminary mc80f0208/16/24 mar. 2005 ver 0.2 7 5. pin function v dd : supply voltage. v ss : circuit ground. av dd : supply voltage to the ladder resistor of adc circuit. reset : reset the mcu. x in : input to the inverting oscillator amplifier and input to the in- ternal main clock operating circuit. x out : output from the inverting oscillator amplifier. r00~r07 : r0 is an 8-bit cmos bidi rectional i/o port. r0 pins with 1 or 0 written to the r0 po rt direction register r0io can be used as outputs or inputs. the in ternal pull-up resi stor can be con- nected by using the pull-up selection register 0 (pu0). r10~r13, r15 : r1 is an 5-bit cmos bidirectional i/o port. r1 pins with 1 or 0 written to the r1 port directi on register r1io can be used as outputs or inputs. the internal pull-up resistor can be connected by using the pull-up selection register 1 (pu1). in addition, r1 serves the functi ons of the various following spe- cial features such as int0 (ext ernal interrupt 0), int1 (external interrupt 1), int2 (external interrupt 2), buzo (buzzer driver output), ec0 (event counter input 0). r30~r33 : r3 is an 4-bit cmos bidi rectional i/o port. r3 pins with 1 or 0 written to the r3 po rt direction register r3io can be used as outputs or inputs. r3 ope rates as the high current output port with typical 20ma at low level output. in addition, r3 serves the functi ons of the following special fea- tures such as aclk1 (uart1 asynchronous serial clock input), rxd1 (uart1 data input), txd1 (uart1 data output). r40~r47 : r4 is an 8-bit cmos bidirectional i/o port. r4 pins with 1 or 0 written to the r4 po rt direction regi ster r4io can be used as outputs or inputs. the inte rnal pull-up resistor can be con- nected by using the pull-up se lection register 4 (pu4). in addition, r4 serves the functi ons of the various following spe- cial features such as sck (serial clock), si (seria l data input), so (serial data output), aclk0 (uart1 asynchr onous serial clock input), rxd0 (uart0 data input), txd0 (uart0 data output). r50, r51, r54 : r5 is an 3-bit cmos bidirectional i/o port. r5 pins with 1 or 0 written to the r5 port direction register r5io can be used as outputs or inputs. in addition, r5 serves the functi ons of the various following spe- cial features such as int3 (e xternal interrupt 3), ec1 (event counter input 1), pwm3o (pwm output 3)/t3o(timer3 com- pare output). r60~r67 : r6 is an 8-bit cmos bidirectional i/o port. r6 pins with 1 or 0 written to the r6 po rt direction regi ster r6io can be used as outputs or inputs. in addition, r6 serves the functions of the adc analog input port an[7:0].
mc80f0208/16/24 preliminary 8 mar. 2005 ver 0.2 5.1 pin description 5.1.1 normal function pin description pin name in/out function initial state alternate function r00~r07 i/o port0 8-bit i/o port. can be set in input or output mode in 1-bit units. internal pull-up resistor pu0 can be used via software. input - r10 i/o port 1. 5-bit i/o port. can be set in input or output mode in 1-bit units. internal pull-up resistor pu1 can be used via software. input int0 r11 int1 r12 int2 r13 buzo r15 ec0 r30 i/o port 3. 4-bit i/o port. can be set in input or output mode in 1-bit units. input - r31 aclk1 r32 rxd1 r33 txd1 r40 i/o port 4. 8-bit i/o port. can be set in input or output mode in 1-bit units. internal pull-up resistor pu4 can be used via software. input - r41 - r42 sck r43 si r44 so r45 aclk0 r46 rxd0 r47 txd0 r50 i/o port 5. 3-bit i/o port. can be set in input or output mode in 1-bit units. input int3 r51 ec1 r54 pwm3o/t3o r60~r67 i/o port 6. 8-bit i/o port. can be set in input or output mode in 1-bit units. input an0~an7 reset i system reset input. input - x in i crystal connection for main system clock oscillation. input - x out o output - av dd - analog power/reference voltag e input to a/d converter. set the same potential as vdd. -- v dd - positive power supply. - - v ss - ground potential. - - table 5-1 normal function pin description
preliminary mc80f0208/16/24 mar. 2005 ver 0.2 9 5.1.2 alternate func tion pin description pin name in/out function initial state shared pin int0 i valid edges(rising, falling, or both ri sing and falling) can be specified. external interrupt request input. input r10 int1 r11 int2 r12 int3 r50 buzo o buzzer output input r13 ec0 i timer0 event counter input input r15 ec1 i timer2 event counter input input r51 sck i/o serial clock input/output of serial interface. input r42 si i serial data input of serial interface. input r43 so o serial data output of se rial interface. input r44 aclk0 i asynchronous serial interf ace serial clock input. input r45 rxd0 i asynchronous serial interface serial data input. input r46 txd0 o asynchronous serial interface serial data output. input r47 aclk1 i asynchronous serial interface serial clock input2. input r31 rxd1 i asynchronous serial interface serial data input2. input r32 txd1 o asynchronous serial interface serial data output2. input r33 pwm3o o timer3 pwm output output r54 t3o timer3 compare output an0~an7 i analog input channel 0 ~ 7 for a/d converter. input r60~r67 table 5-2 alternate function pin description
mc80f0208/16/24 preliminary 10 mar. 2005 ver 0.2 6. port structures r00~r07, r40, r41 r10(int0)~ r12(int2), r15(ec0), r43(si), r45(aclk0), r46(rxd0) r13(buzo), r47(txd0) r30 v dd v ss pin data reg. direction reg. pull-up tr. pull-up reg. v dd data bus v dd v ss mux rd v dd v ss pin data reg. direction reg. rd rxd0, aclk0 int_en, ec_en pull-up tr. pull-up reg. v dd noise filter data bus v dd v ss mux int,ec,si, si_en, aclk0_en, rxd0_en v dd v ss pin data reg. direction reg. pull-up tr. pull-up reg. v dd buzo_en,txd0_en data bus buzo,txd0 v dd v ss mux mux rd v dd v ss pin data reg. direction reg. data bus v dd v ss mux rd
preliminary mc80f0208/16/24 mar. 2005 ver 0.2 11 r33(txd1) r42(sck) r44(so, ioswin) r31(aclk1), r32(rx d1), r50(int3), r51(ec1) v dd v ss pin data reg. direction reg. txd1_en data bus txd1 v dd v ss mux mux rd v dd v ss pin data reg. direction reg. sck scki_en pull-up tr. pull-up reg. v dd noise filter data bus sck scko_en v dd v ss mux mux rd v dd v ss pin data reg. direction reg. si pull-up tr. pull-up reg. v dd noise filter data bus so so_en ioswin_en ioswin_en v dd v ss mux mux rd v dd v ss pin data reg. direction reg. rd aclk1, rxd1 int3_en, ec1_en noise filter data bus v dd mux int3, ec1 aclk1_en, rxd1_en
mc80f0208/16/24 preliminary 12 mar. 2005 ver 0.2 r54(pwm3o/t3o) r60~r67(an0~an7) x in , x out reset v dd v ss pin data reg. direction reg. pwm3_en data bus pwm3o v dd v ss mux mux rd v dd v ss pin data reg. direction reg. rd an[7:0] adc_en & ch_sel data bus v dd v ss mux x out v dd v ss x in v dd v ss v ss stop main clock pin v dd v ss internal reset mask only
preliminary mc80f0208/16/24 mar. 2005 ver 0.2 13 7. electrical characteristics 7.1 absolute maximum ratings note: stresses above those listed under ?absolute maxi- mum ratings? may cause permanent damage to the de- vice. this is a stress rating only and functional operation of the device at any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for ex- tended periods may affect device reliability. 7.2 recommended operating conditions 7.3 a/d converter characteristics (t a =-40~85 c, v ss =0v, v dd = av dd = 2.7~5.5v @f xin =4mhz) parameter symbol rating unit note supply voltage v dd -0.3 ~ +6.5 v - av dd v dd - 0.3 ~ v dd +0.3 v- normal votagae pin v i -0.3 ~ v dd +0.3 v voltage on any pin with respect to ground (v ss ) v o -0.3 ~ v dd +0.3 v i oh 10 ma maximum output current sourced by (i oh per i/o pin) i oh 80 ma maximum current ( i oh ) i ol 20 ma maximum current sunk by (i ol per i/o pin) i ol 160 ma maximum current ( i ol ) total power dissipation f xin 600 mw - storage temperature t stg -65 ~ +150 c c parameter symbol condition specifications unit min. max. supply voltage v dd f xin = 0.4 ~ 12mhz 4.5 5.5 v f xin = 0.4 ~ 8mhz 2.7 5.5 v operating temperature t opr v dd = 4.5 ~ 5.5v -40 85 c parameter symbol conditions min. typ. max. unit resolution - --10-bit total accuracy - av dd = v dd = 5.12v f xin = 4mhz -- 3lsb intergral linearity error ile -- 2lsb differential linearity error dle -- 2 lsb zero offset error zoe -- 2 lsb full scale error fse -- 2 lsb conversion time t con 10bit conversion f xin = 4mhz 13* - - s
mc80f0208/16/24 preliminary 14 mar. 2005 ver 0.2 7.4 dc electrical characteristics (t a =-40~85 c, v dd =5.0v 10%, v ss =0v, f xin =8mhz) analog input voltage v an - v ss - av dd v analog power supply av dd --- v dd v analog ground v ss - v ss - v ss +0.3 v analog input current i adin av dd =v dd =5.12v --10 a analog block current i adc av dd =v dd =5.12v - 200 300 a parameter symbol conditions min. typ. max. unit note : 4mhz(f xin ) / 2 2 x 13cycle = 13us parameter symbol pin/condition min. typ. max. unit input high voltage v ih1 int0, int1, int2, int3, ec0, ec1, si, sck, aclk0, aclk1, rxd0, rxd1, reset 0.8v dd - v dd +0.3 v v ih2 r0, r1, r3, r4, r5, r6 0.7v dd - v dd +0.3 v v ih3 x in 0.8v dd - v dd +0.3 v input low voltage v il1 int0, int1, int2, int3, ec0, ec1, si, sck, aclk0,aclk1, rxd0, rxd1, reset -0.3 - 0.2v dd v v il2 r0, r1, r3, r4, r5, r6 -0.3 - 0.3v dd v v il3 x in -0.3 - 0.2v dd v output high voltage v oh1 r0, r1, r3, r4, r5, r6 (i oh =-0.7ma) v dd -0.4 --v v oh2 x out (i oh =-50 a) v dd -0.5 --v output low voltage v ol1 r0, r1, r3, r4, r5, r6 (i ol =1.6ma) - -0.4v v ol2 x out (i ol =50 a) - -0.5v high current i ol r3 (v ol =1v) --20ma input high leakage current i ih r0, r1, r3, r4, r5, r6 - - 1 a input low leakage current i il r0, r1, r3, r4, r5, r6 -1 - - a pull-up resistor rpu r0, r1, r4 10 - 100 k ? osc feedback resistor r x x in , x out 0.45 - 4.5 m ? internal rc wdt period (rcwdt) i il v dd =4.5v 33 - 100 s hysteresis v t int0, int1, int2, int3, ec0, ec1, si, sck, aclk0, aclk1, rxd0,rxd1 0.3 - 0.8 v power fail detect voltage v pfd 2.2 2.7 3.2 v 2.5 3.0 3.5 v 1.9 2.4 2.9 v
preliminary mc80f0208/16/24 mar. 2005 ver 0.2 15 power supply current i dd1 active mode, x in =8mhz --15ma i sleep sleep mode, x in =8mhz --6ma i stop stop mode, oscillator stop, x in =4mhz --5 a i rcwdt stop mode, oscillator stop, x in =8mhz --40 a parameter symbol pin/condition min. typ. max. unit
mc80f0208/16/24 preliminary 16 mar. 2005 ver 0.2 7.5 ac characteristics (t a =-40~85 c, v dd =5v 10%, v ss =0v) figure 7-1 timing chart parameter symbol pins specifications unit min. typ. max. operating frequency f xin x in 0.4 - 12 mhz oscillation stabilizing time (4mhz) t st x in , x out --20ms external clock pulse width t cpw x in 35 - - ns external clock transi- tion time t rcp, t fcp x in --20ns interrupt pulse width t iw int0, int1, in t2, int3 2 - - t sys reset input width t rst reset 8- - t sys event counter input pulse width t ecw ec0, ec1 2 - - t sys event counter transi- tion time t rec, t fec ec0, ec1 - - 20 ns t rcp t fcp x in int0~int3 0.5v v dd -0.5v 0.2v dd 0.8v dd 0.2v dd reset t rec t fec 0.2v dd 0.8v dd ec0, ec1 t iw t iw t rst t ecw t ecw t sys = 1/f xin t cpw t cpw
preliminary mc80f0208/16/24 mar. 2005 ver 0.2 17 7.6 serial interface timing characteristics (t a =-40~+85 c, v dd =5v 10%, v ss =0v, f xin =8mhz) figure 7-2 serial i/o timing chart parameter symbol pins specifications unit min. typ. max. serial input clock pulse t scyc sck 2t sys +200 --ns serial input clock pulse width t sckw sck t sys +70 --ns serial input clock pulse transition time t fsck t rsck sck - - 30 ns serial input pulse transition time t fsin t rsin si - - 30 ns serial input setup time (external sck) t sus si 100 - - ns serial input setup time (internal sck) t sus si 200 - ns serial input hold time t hs si t sys +70 -ns serial output clock cycle time t scyc sck 4t sys - 16t sys ns serial output clock pulse width t sckw sck t sys -30 ns serial output clock pulse transition time t fsck t rsck sck 30 ns serial output delay time s out so 100 ns sck si 0.2v dd so 0.2v dd 0.8v dd t scyc t sckw t sckw t rsck t fsck 0.8v dd t sus t hs t ds 0.2v dd 0.8v dd t rsin t fsin
mc80f0208/16/24 preliminary 18 mar. 2005 ver 0.2 7.7 typical characteristic curves this graphs and tables provided in this section are for design guidance only and are not tested or guaranteed. in some graphs or tables the data presented are out- side specified operating ra nge (e.g. outside specified v dd range). this is for information only and devices are guaranteed to operate properly only within the specified range. the data presented in this section is a statistical summary of data collected on units from different lots over a period of time. ?typ- ical? represents the mean of the distribution while ?max? or ?min? represents (mean + 3 ) and (mean ? 3 ) respectively where is standard deviation i oh ? v oh -12 -9 -6 -3 0 0.5 1.0 1.5 2.0 (v) t a =25 c v dd =5.0v r0,r1,r3~r6 pins (ma) i oh v dd -v oh i ol ? v ol1 40 30 20 10 0 (ma) i ol 0.5 1.0 1.5 2.0 2.5 v ol (v) t a =25 c v dd =5.0v r0~r2, r4~r6 pins i oh ? v oh -12 -9 -6 -3 0 0.5 1.0 1.5 2.0 (v) t a =25 c v dd =3.0v (ma) i oh v dd -v oh i ol ? v ol1 20 15 10 5 0 (ma) i ol 0.5 1.0 1.5 2.0 v ol (v) t a =25 c v dd =3.0v r0,r1, r4~r6 pins i ol ? v ol2 40 30 20 10 0 (ma) i ol 0.5 1.0 1.5 2.0 2.5 v ol (v) t a =25 c v dd =5.0v r3 pin i ol ? v ol2 20 15 10 5 0 (ma) i ol 0.5 1.0 1.5 2.0 v ol (v) t a =25 c v dd =3.0v r3 pin 2.5 r0,r1,r3~r6 pins
preliminary mc80f0208/16/24 mar. 2005 ver 0.2 19 10 6 4 2 0 (mhz) f xin 23 45 6 v dd (v) operating area 8 7 14 12 t a = -40~85 c 1 16 t a =25 c i dd ? v dd 10 7.5 5 2.5 0 (ma) i dd 23 45 6 v dd (v) main active mode i sleep ? v dd 4 3 2 1 0 (ma) i dd 23 45 6 v dd (v) main active mode 4mhz f xin = 12mhz i stop ? v dd 4 3 2 1 0 ( a) i dd 23 45 6 v dd (v) main active mode 4mhz f xin = 12mhz 8mhz 8mhz f xin = 12mhz, 8mhz, 4mhz t a =25 c t a =25 c actual operating area 2.1~7.0v @ (0.2~8mhz) 2.6~7.0v @ (0.2~16mhz) spec operating area 2.7~5.5v @ (0.4~8mhz) 4.5~5.5v @ (0.4~12mhz)
mc80f0208/16/24 preliminary 20 mar. 2005 ver 0.2 8. memory organization the mc80f0208/16/24 has separate address spaces for program memory and data memory. progr am memory can only be read, not written to. it can be up to 48k bytes of program memory. data memory can be read and wr itten to up to 1024 bytes includ- ing the stack area. 8.1 registers this device has six registers th at are the program counter (pc), a accumulator (a), two index regi sters (x, y), the stack pointer (sp), and the program status word (psw). the program counter consists of 16-bit register. figure 8-1 configuration of registers accumulator: the accumulator is the 8-bit general purpose reg- ister, used for data operation such as transfer, temporary saving, and conditional judgement, etc. the accumulator can be used as a 16-bit register with y register as shown below. figure 8-2 configuration of ya 16-bit register x, y registers : in the addressing mode which uses these index registers, the register contents are added to the specified address, which becomes the actual address. these modes are extremely ef- fective for referencing subroutine tables and memory tables. the index registers also have increment, decrement, comparison and data transfer functions, and they can be used as simple accumula- tors. stack pointer : the stack pointer is an 8-bit register used for oc- currence interrupts and calling out subroutines. stack pointer identifies the location in the stack to be accessed (save or restore). generally, sp is au tomatically upda ted when a subroutine call is executed or an interrupt is accepted . however, if it is used in ex- cess of the stack area permitted by the data memory allocating configuration, the user-pro cessed data may be lost. the stack can be located at any position within 100 h to 1ff h of the internal data memory. the sp is not initialized by hardware, requiring to write the initial value (the location with which the use of the stack starts) by using the initialization routine. normally, the initial value of ?ff h ? is used. note: the stack pointer must be initialized by software be- cause its value is undefined after reset. example: to initialize the sp ldx #0ffh txsp ; sp ffh program counter : the program counter is a 16-bit wide which consists of two 8-bit registers, pch and pcl. this counter indi- cates the address of the next inst ruction to be executed. in reset state, the program counter ha s reset routine address (pc h :0ff h , pc l :0fe h ). program status word : the program status word (psw) con- tains several bits that reflect the current state of the cpu. the psw is described in figure 8-3. it contains the negative flag, the overflow flag, the break flag the half carry (for bcd opera- tion), the interrupt enable flag, th e zero flag, and the carry flag. [carry flag c] this flag stores any carry or borrow from the alu of cpu after an arithmetic operation and is al so changed by the shift instruc- tion or rotate instruction. [zero flag z] this flag is set when the result of an arithmetic operation or data transfer is ?0? and is cleared by any other result. accumulator x register y register stack pointer program counter program status word x a sp y pcl psw pch two 8-bit registers can be used as a ?ya? 16-bit register y a y a sp 01 h stack address (100 h ~ 1ff h ) bit 15 bit 0 87 hardware fixed 00 h ~ff h
preliminary mc80f0208/16/24 mar. 2005 ver 0.2 21 figure 8-3 psw (program status word) register [interrupt disable flag i] this flag enables/disables all interrupts except interrupt caused by reset or software brk instruct ion. all interrupts are disabled when cleared to ?0?. this flag immediately becomes ?0? when an interrupt is served. it is set by the ei instruction and cleared by the di instruction. [half carry flag h] after operation, this is set when there is a carry from bit 3 of alu or there is no borrow from bit 4 of alu. this bit can not be set or cleared except clrv instru ction with overflow flag (v). [break flag b] this flag is set by software brk instruction to distinguish brk from tcall instruction with the same vector address. [direct page flag g] this flag assigns ram page for di rect addressing mode. in the di- rect addressing mode, addressi ng area is from zero page 00 h to 0ff h when this flag is "0". if it is set to "1", addressing area is assigned 100 h to 1ff h . it is set by setg instruction and cleared by clrg. [overflow flag v] this flag is set to ?1? when an overflow occurs as the result of an arithmetic operation involving signs. an overflow occurs when the result of an addition or subtraction exceeds +127(7f h ) or - 128(80 h ). the clrv instruction clears the overflow flag. there is no set instruction. when the bi t instruction is executed, bit 6 of memory is copied to this flag. [negative flag n] this flag is set to match the sign bit (bit 7) status of the result of a data or arithmetic operation. when the bit instruction is exe- cuted, bit 7 of memory is copied to this flag. n negative flag v g b h i z c msb lsb reset value: 00 h psw overflow flag brk flag carry flag receives zero flag interrupt enable flag carry out half carry fl ag receives carry out from bit 1 of addition operlands select direct page when g=1, page is selected to ?page 1?
mc80f0208/16/24 preliminary 22 mar. 2005 ver 0.2 figure 8-4 stack operation 8.2 program memory a 16-bit program counter is capable of addressing up to 64k bytes, but this device has 32/48k bytes program memory space only physically implemented. ac cessing a location above ffff h will cause a wrap-around to 0000 h . figure 8-5, shows a map of program memory. after reset, the cpu begins execution from reset vector which is stored in ad- dress fffe h and ffff h as shown in figure 8-6. as shown in figure 8-5, each ar ea is assigned a fixed location in program memory. program memory area contains the user pro- gram at execution of a call/tcall/pcall pcl pch 01fc sp after execution sp before execution 01fd 01fd 01fe 01ff 01ff push down at acceptance of interrupt pcl pch 01fc 01fc 01fd 01fe 01ff 01ff push down psw at execution of ret instruction pcl pch 01fc 01ff 01fd 01fe 01ff 01fd pop up at execution of ret instruction pcl pch 01fc 01ff 01fd 01fe 01ff 01fc pop up psw 0100h 01ffh stack depth at execution of push instruction a 01fc 01fe 01fd 01fe 01ff 01ff push down sp after execution sp before execution push a (x,y,psw) at execution of pop instruction a 01fc 01ff 01fd 01fe 01ff 01fe pop up pop a (x,y,psw)
preliminary mc80f0208/16/24 mar. 2005 ver 0.2 23 . figure 8-5 program memory map page call (pcall) area contai ns subroutine program to reduce program byte length by using 2 bytes pcall instead of 3 bytes call instruction. if it is frequen tly called, it is more useful to save program byte length. table call (tcall) causes the cpu to jump to each tcall ad- dress, where it commences the execution of the service routine. the table call service area sp aces 2-byte fo r every tcall: 0ffc0 h for tcall15, 0ffc2 h for tcall14, etc., as shown in figure 8-7. example: usage of tcall the interrupt causes the cpu to jump to specific location, where it commences the execution of the service routine. the external interrupt 0, for example, is assigned to location 0fffc h . the in- terrupt service locations sp aces 2-byte interval: 0fffa h and 0fffb h for external interrupt 1, 0fffc h and 0fffd h for ex- ternal interrupt 0, etc. any area from 0ff00 h to 0ffff h , if it is not going to be used, its service location is availabl e as general purpose program mem- ory. figure 8-6 interrupt vector area interrupt vector area c000 h feff h ff00 h ffc0 h ffdf h ffe0 h ffff h pcall area e000 h a000 h tcall area mc80f0216, 16k rom mc80f0224, 24k rom mc80f0208, 8k rom lda #5 tcall 0fh ; 1byte instruction :; instead of 3 bytes :; normal call ; ;table call routine ; func_a: lda lrg0 ret ; func_b: lda lrg1 ret ; ;table call add. area ; org 0ffc0h ; tcall address area dw func_a dw func_b 1 2 0ffe0 h e2 address vector area memory e4 e6 e8 ea ec ee f0 f2 f4 f6 f8 fa fc fe basic interval timer watch / watchdog timer interrupt a/d converter timer/counter 4 interrupt external interrupt 3 serial input/output (sio) external interrupt 1 external interrupt 0 reset external interrupt 2 timer/counter 3 interrupt timer/counter 0 interrupt uart0 rx/tx interrupt uart1 rx/tx interrupt timer/counter 1 interrupt timer/counter 2 interrupt
mc80f0208/16/24 preliminary 24 mar. 2005 ver 0.2 figure 8-7 pcall and tcall memory area pcall rel 4f35 pcall 35h tcall n 4a tcall 4 0ffc0 h c1 address program memory c2 c3 c4 c5 c6 c7 c8 0ff00 h address pcall area memory 0ffff h pcall area (256 bytes) * means that the brk software interrupt is using same address with tcall0. note: tcall 15 tcall 14 tcall 13 tcall 12 tcall 11 tcall 10 tcall 9 tcall 8 tcall 7 tcall 6 tcall 5 tcall 4 tcall 3 tcall 2 tcall 1 tcall 0 / brk * c9 ca cb cc cd ce cf d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 da db dc dd de df 4f ~ ~ ~ ~ next 35 0ff35 h 0ff00 h 0ffff h 11111111 11010110 01001010 pc: fh fh dh 6h 4a ~ ~ ~ ~ 25 0ffd6 h 0ff00 h 0ffff h d1 next 0ffd7 h ? ? ? 0d125 h reverse
preliminary mc80f0208/16/24 mar. 2005 ver 0.2 25 example: the usage softwa re example of vector address for mc80f0208/16/24 . ;interrupt vector table org 0ffe0h dw bit_timer ; bit dw watch_wdt ; wdt & wt dw adc ; ad converter dw timer4 ; timer-4 dw timer3 ; timer-3 dw timer2 ; timer-2 dw timer1 ; timer-1 dw timer0 ; timer-0 dw sio ; serial interface dw uart1 ; uart1 rx/tx dw uart0 ; uart0 rx/tx dw int3 ; ext int.3 dw int2 ; ext int.2 dw int1 ; ext int.1 dw int0 ; ext int.0 dw reset ; reset org 0a000h ; 24k bytes rom start address ;******************************************* ; main program * ;******************************************* reset: di ;disable all interrupt ramclear: ldx #00h ;user ram start address load ! ldy #0 ramclr1: lda #00h ;page0 ram clear(0000h ~ 00bfh) sta {x}+ ; cmpx #0c0h ; bne ramclr1 ; inc y ; sty !rpr ;page1 ram select setg ;g-flag set ! ldx #00h ramclr2: lda #00h sta {x}+ cmpx #00h bne ramclr2 inc y cmpy #4 bcs ramclr3 ;page1 ~ page3 clear(0100h ~ 03ffh) sty !rpr setg bra ramclr2 ramclr3: sty !rpr ;page4 clear(0400h ~ 043fh) setg lda #00h ;a <-- #0 sta {x}+ cmpx #40h ; bne ramclr3 clrg ;g-flag clear ! ldx #0ffh txsp ;initial stack point (01ffh)
mc80f0208/16/24 preliminary 26 mar. 2005 ver 0.2 8.3 data memory figure 8-8 shows the internal data memory space available. data memory is divided into three gr oups, a user ram, control regis- ters, and stack memory. figure 8-8 data memory map user memory the mc80f0208/16/24 has 1024 8 bits for the user memory (ram). ram pages are selected by rpr (see figure 8-9). note: after setting rpr(ram page select register), be sure to execute setg instru ction. when executing clrg instruction, be selected page0 regardless of rpr. control registers the control registers are used by the cpu and peripheral function blocks for controlling the desire d operation of the device. there- fore these registers contain control and status bits for the interrupt system, the timer/ counters, anal og to digital converters and i/o ports. the control registers are in address range of 0c0 h to 0ff h . note that unoccupied addresses may not be implemented on the chip. read accesses to these addresses will in general return ran- dom data, and write accesses will have an indeterminate effect. more detailed informations of ea ch register are explained in each peripheral section. note: write only registers can not be accessed by bit ma- nipulation instruction. do not use read-modify-write instruc- tion. use byte manipulation instruction, for example ?ldm?. example; to write at ckctlr ldm clctlr,#0ah ;divide ratio( 32) stack area the stack provides the area where the return address is saved be- fore a jump is performed during the processing routine at the ex- ecution of a subroutine call in struction or the acceptance of an interrupt. when returning from the processi ng routine, executing the sub- routine return instruction [ret] re stores the contents of the pro- gram counter from the stack; executing the interrupt return instruction [reti] restores the c ontents of the program counter and flags. the save/restore locations in the stack are determined by the stack pointed (sp). the sp is au tomatically decreased after the saving, and increased before the restoring. this means the value of the sp indicates the stack lo cation number for the next save. refer to figure 8-4 on page 22. figure 8-9 rpr(ram page select register) user memory control registers 0000 h 00bf h 00c0 h page0 page1 (when ?g-flag=0?, this page0 is selected) or stack area user memory user memory user memory user memory page2 page3 00ff h 0100 h 01ff h 0200 h 02ff h 0300 h 03ff h 0400 h 03bf h 03c0 h 04ff h 043f h 0440 h page4 (192bytes) (256bytes) (256bytes) (256bytes) (64bytes) not used system clock source select 000 : page0 001 : page1 initial value: ---- -000 b address: 0e1 h rpr 010 : page2 011 : page3 - 76543210 - - r/w r/w r/w rpr2 -- rpr1 rpr0 100 : page4 -
preliminary mc80f0208/16/24 mar. 2005 ver 0.2 27 address register name symbol r/w initial value addressing mode 76543210 00c0 r0 port data register r0 r/w 00000000 byte, bit 1 00c1 r0 port i/o direction register r0io w 00000000 byte 2 00c2 r1 port data register r1 r/w 00000000 byte, bit 00c3 r1 port i/o direction register r1io w 00000000 byte 00c4 reserved 00c5 reserved 00c6 r3 port data register r3 r/w 00000000 byte, bit 00c7 r3 port i/o direction register r3io w 00000000 byte 00c8 r4 port data register r4 r/w 00000000 byte, bit 00c9 r4 port i/o direction register r4io w 00000000 byte 00ca r5 port data register r5 r/w - - - 0 0 0 0 0 byte, bit 00cb r5 port i/o direction register r5io w - - - 0 0 0 0 0 byte 00cc r6 port data register r6 r/w 00000000 byte, bit 00cd r6 port i/o direction register r6io w 00000000 byte 00ce reserved 00cf reserved 00d0 timer 0 mode control register tm0 r/w - - 000000 byte, bit 00d1 timer 0 register t0 r 00000000 byte timer 0 data register tdr0 w 11111111 timer 0 capture data register cdr0 r 0 0 000000 00d2 timer 1 mode control register tm1 r/w 00000000 byte, bit 00d3 timer 1 data register tdr1 w 11111111 byte 00d4 timer 1 register t1 r 00000000 byte timer 1 capture data register cdr1 r 0 0 000000 00d5 reserved 00d6 timer 2 mode control register tm2 r/w - - 000000 byte, bit 00d7 timer 2 register t2 r 00000000 byte timer 2 data register tdr2 w 11111111 timer 2 capture data register cdr2 r 0 0 000000 00d8 timer 3 mode control register tm3 r/w 00000000 byte, bit 00d9 timer 3 data register tdr3 w 11111111 byte timer 3 pwm period register t3ppr w 11111111 table 8-1 control registers
mc80f0208/16/24 preliminary 28 mar. 2005 ver 0.2 00da timer 3 register t3 r 00000000 byte timer 3 pwm duty register t3pdr r/w 00000000 timer 3 capture data register cdr3 r 0 0 000000 00db timer 3 pwm high register t3pwhr w - - - - 0 0 0 0 byte 00dc timer 4 mode control register tm4 r/w - - 000000 byte, bit 00dd timer 4 low register t4l r 00000000 byte timer 4 low data register tdr4l w 11111111 timer 4 capture low data register cdr4l r 00000000 00de timer 4 high register t4h r 00000000 byte timer 4 high data register tdr4h w 11111111 timer 4 capture high data register cdr4h r 0 0 000000 00df interrupt flag register ifr r/w - - 000000 byte, bit 00e0 buzzer driver register buzr w 11111111 byte 00e1 ram page selection register rpr r/w -----000 byte, bit 00e2 sio mode control register siom r/w 00000001 byte, bit 00e3 sio data shift register sior r/w undefined byte, bit 00e4 reserved 00e5 reserved 00e6 uart0 mode register asimr0 r/w 0 0 0 0 - 0 0 - byte, bit 00e7 uart0 status register asisr0 r -----000 byte 00e8 uart0 baud rate generator control register brgcr0 r/w - 0010000 byte, bit 00e9 uart0 receive buffer register rxr0 r 00000000 byte uart0 transmit shift register txr0 w 11111111 00ea interrupt enable register high ienh r/w 00000000 byte, bit 00eb interrupt enable register low ienl r/w 00000000 byte, bit 00ec interrupt request register high irqh r/w 0 0 000000 byte, bit 00ed interrupt request register low irql r/w 0 0 000000 byte, bit 00ee interrupt edge selection register ieds r/w 00000000 byte, bit 00ef a/d converter mode control register adcm r/w 00000001 byte, bit 00f0 a/d converter result high register adcrh r(w) 0 1 undefined byte 00f1 a/d converter result lo w register adcrl r undefined byte 00f2 basic interval timer register bitr r undefined byte clock control register ckctlr w 0 - 010111 00f3 reserved address register name symbol r/w initial value addressing mode 76543210 table 8-1 control registers
preliminary mc80f0208/16/24 mar. 2005 ver 0.2 29 00f4 watch dog timer register wdtr w 01111111 byte watch dog timer data register wdtdr r undefined 00f5 stop & sleep mode control register sscr w 00000000 byte 00f6 watch timer mode register wtmr r/w 0 - - 0 0 0 0 0 byte, bit 00f7 pfd control register pfdr r/w -----000 byte, bit 00f8 port selection register 0 psr0 w 00000000 byte 00f9 port selection register 1 psr1 w - - - - 0 0 0 0 byte 00fa reserved 00fb reserved 00fc pull-up selection register 0 pu0 w 00000000 byte 00fd pull-up selection register 1 pu1 w 00000000 byte 00fe pull-up selection register 4 pu4 w 00000000 byte 00ff reserved 0ee6 uart1 mode register asimr1 r/w 0 0 0 0 - 0 0 - byte, bit 0ee7 uart1 status register asisr1 r -----000 byte 0ee8 uart1 baud rate generator control register brgcr1 r/w - 0010000 byte, bit 0ee9 uart1 receive buffer register rxr1 r 00000000 byte uart1 transmit shift register txr1 w 11111111 address register name symbol r/w initial value addressing mode 76543210 table 8-1 control registers the ?byte? means registers are controlled by only byte manipulation instruction. do not use bit manipulation 1. the ?byte, bit? means registers are controll ed by both bit and byte m anipulation instruction. 2. instruction such as set1, clr1 etc. if bit m anipulation instruction is used on these registers, content of other seven bits are may varied to unwanted value. *the mark of ?-? means this bit location is reserved. caution) the r/w register except t1pdr a nd t3pdr are both can be byte and bit manipulated. 3. the uart1 control register asimr1,asisr1, brgcr1,rxr1 and txr1 are located at ee6h ~ ee9h address. these address must be accessed(read and written) by absolute addressing manipulation instruction.
mc80f0208/16/24 preliminary 30 mar. 2005 ver 0.2 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0c0h r0 r0 port data register 0c1h r0io r0 port direction register 0c2h r1 r1 port data register 0c3h r1io r1 port direction register 0c4h reserved 0c5h reserved 0c6h r3 r3 port data register 0c7h r3io r3 port direction register 0c8h r4 r4 port data register 0c9h r4io r4 port direction register 0cah r5 - - - r5 port data register 0cbh r5io - - - r5 port direction register 0cch r6 r6 port data register 0cdh r6io r6 port direction register 0ceh reserved 0cfh reserved 0d0h tm0 - - cap0 t0ck2 t0ck1 t0ck0 t0cn t0st 0d1h t0/tdr0/ cdr0 timer0 register / timer0 data register / timer0 capture data register 0d2h tm1 - 16bit - cap1 t1ck1 t1ck0 t1cn t1st 0d3h tdr1 timer1 data register 0d4h t1/cdr1 timer1 register / timer1 capture data register 0d5h pwm1hr - - - - timer1 pwm high register 0d6h tm2 - - cap2 t2ck2 t2ck1 t2ck0 t2cn t2st 0d7h t2/tdr2/ cdr2 timer2 register / timer2 data register / timer2 capture data register 0d8h tm3 pol 16bit pwm3e cap3 t3ck1 t3ck0 t3cn t3st 0d9h tdr3/ t3ppr timer3 data register / ti mer3 pwm period register 0dah t3/cdr3/ t3pdr timer3 register / timer3 capture data register / timer3 pwm duty register 0dbh pwm3hr - - - - timer3 pwm high register 0dch tm4 - - cap4 t4ck2 t4ck1 t4ck0 t4cn t4st 0ddh t4l/ tdr4l/ cdr4l timer4 register low / timer4 data register low / timer4 capture data register low table 8-2 control register function description
preliminary mc80f0208/16/24 mar. 2005 ver 0.2 31 0deh t4h/ tdr4h/ cdr4h timer4 register high / timer4 data register high / timer4 capture data register high 0dfh ifr - - rx0iof tx0iof rx1iof tx1iof wtiof wdtiof 0e0h buzr buck1 buck0 bur5 bur4 bur3 bur2 bur1 bur0 0e1h rpr - - - - - rpr2 rpr1 rpr0 0e2h siom pol iosw sm1 sm0 sck1 sck0 siost siosf 0e3h sior sio data shift register 0e4h reserved 0e5h reserved 0e6h asimr0 txe0 rxe0 ps01 ps00 - sl0 isrm0 - 0e7h asisr0 - - - - - pe0 fe0 ove0 0e8h brgcr0 - tps02 tps01 tps00 mld03 mld02 mld01 mld00 0e9h rxr0 uart0 receive buffer register txr0 uart0 transmit shift register 0eah ienh int0e int1e int2e int3e rxe txe sioe t0e 0ebh ienl t1e t2e t3e t4e adce wdte wte bite 0ech irqh int0if int1if int2if int3if rxif txif sioif t0if 0edh irql t1if t2if t3if t4if adcif wdtif wtif bitif 0eeh ieds ied3h ied3l ied2h ied2l ied1h ied1l ied0h ied0l 0efh adcm aden adck ads3 ads2 ads1 ads0 adst adsf 0f0h adcrh pssel1 pssel0 adc8 - - - adc result reg. high 0f1h adcrl adc result register low 0f2h bitr 1 basic interval timer data register ckctlr 1 adrst - rcwdt wdton btcl bts2 bts1 bts0 0f3h reserved 0f4h wdtr wdtcl 7-bit watchdog timer register wdtdr watchdog timer data register (counter register) 0f5h sscr stop & sleep mode control register 0f6h wtmr wten - - wtin2 wtin1 wtin0 wtck1 wtck0 0f7h pfdr - - - - - pfden pfdm pfds 0f8h psr0 pwm3o - ec1e ec0e int3e int2e int1e int0e 0f9h psr1 - - - - xten buzo - - 0fah reserved 0fbh reserved 0fch pu0 r0 pull-up selection register 0fdh pu1 r1 pull-up selection register 0feh pu4 r4 pull-up selection register address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 table 8-2 control register function description
mc80f0208/16/24 preliminary 32 mar. 2005 ver 0.2 8.4 addressing mode the mc800 series mcu uses six addressing modes; ? register addressing ? immediate addressing ? direct page addressing ? absolute addressing ? indexed addressing ? register-indirect addressing 8.4.1 register addressing register addressing accesses the a, x, y, c and psw. 8.4.2 immediate addressing #imm in this mode, second byte (opera nd) is accessed as a data imme- diately. example: 0435 adc #35h when g-flag is 1, then ram a ddress is defined by 16-bit address which is composed of 8-bit ram paging register (rpr) and 8-bit immediate data. example: g=1 e45535 ldm 35h,#55h 8.4.3 direct page addressing dp in this mode, a address is sp ecified within direct page. example; g=0 0ffh reserved ee6h 2 asimr1 txe1 rxe1 ps11 ps10 - sl1 isrm1 - ee7h 2 asisr1 - - - - - pe1 fe1 ove1 ee8h 2 brgcr1 - tps12 tps11 tps10 mld13 mld12 mld11 mld10 ee9h 2 rxr1 uart1 receive buffer register txr1 uart1 transmit shift register 1. the register bitr and ckctlr are located at same ad dress. address f2h is read as bitr, written to ckctlr. caution) the registers of dark-shaded area can not be accessed by bit manipulation instruction such as "set1, clr1", but should be accessed by register operation instruction such as "ldm dp,#imm". 2. the uart1 control register asimr1,asisr1, brgcr1,rxr1 and txr1 are located at ee6h ~ ee9h address. these address must be accessed(read and written) by absolute addressing manipulation instruction. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 table 8-2 control register function description 35 a+35h+c a 04 memory e4 0f100h data 55h ~ ~ ~ ~ data 0135h ? 35 0f102h 55 0f101h ?
preliminary mc80f0208/16/24 mar. 2005 ver 0.2 33 c535 lda 35h ;a ram[35h] 8.4.4 absolute addressing !abs absolute addressing sets corres ponding memory data to data, i.e. second byte (operand i) of comm and becomes lower level ad- dress and third byte (operand ii) becomes upper level address. with 3 bytes command, it is pos sible to access to whole memory area. adc, and, cmp, cmpx, cmpy, eor, lda, ldx, ldy, or, sbc, sta, stx, sty example; 0735f0 adc !0f035h ;a rom[0f035h] the operation within data memory (ram) asl, bit, dec, in c, lsr, rol, ror example; addressing accesses the address 0135 h regardless of g-flag. 983501 inc !0135h ;a rom[135h] 8.4.5 indexed addressing x indexed direct page (no offset) {x} in this mode, a address is specified by the x register. adc, and, cmp, eor, lda, or, sbc, sta, xma example; x=15 h , g=1 d4 lda {x} ;acc ram[x]. x indexed direct page, auto increment {x}+ in this mode, a address is specified within direct page by the x register and the content of x is increased by 1. lda, sta example; g=0, x=35 h db lda {x}+ data 35 35h 0e551h data a ? ? ~ ~ ~ ~ c5 0e550h 07 0f100h ~ ~ ~ ~ data 0f035h ? f0 0f102h 35 0f101h ? a+data+c a address: 0f035 98 0f100h ~ ~ ~ ~ data 135h ? 01 0f102h 35 0f101h ? data+1 data ? address: 0135 data d4 115h 0e550h data a ? ? ~ ~ ~ ~
mc80f0208/16/24 preliminary 34 mar. 2005 ver 0.2 x indexed direct page (8 bit offset) dp+x this address value is the second byte (operand) of command plus the data of x -register. and it assigns the memory in direct page. adc, and, cmp, eor, lda, ldy, or, sbc, sta sty, xma, asl, dec, in c, lsr, rol, ror example; g=0, x=0f5 h c645 lda 45h+x y indexed direct page (8 bit offset) dp+y this address value is the second byte (operand) of command plus the data of y-register, which as signs memory in direct page. this is same with above (2). use y register instead of x. y indexed absolute !abs+y sets the value of 16-bit absolute address plus y-register data as memory.this addressing mode can specify memory in whole ar- ea. example; y=55 h d500fa lda !0fa00h+y 8.4.6 indirect addressing direct page indirect [dp] assigns data address to use for accomplishing command which sets memory data (or pair memory) by operand. also index can be used with index register x,y. jmp, call example; g=0 3f35 jmp [35h] x indexed indirect [dp+x] processes memory data as data , assigned by 16-bit pair memory which is determined by pair da ta [dp+x+1][dp+x] operand plus x-register data in direct page. adc, and, cmp, eor, lda, or, sbc, sta example; g=0, x=10 h data db 35h data a ? ? ~ ~ ~ ~ 36h x data 45 3ah 0e551h data a ? ? ~ ~ ~ ~ c6 0e550h 45h+0f5h=13ah ? d5 0f100h data a ? ~ ~ ~ ~ data 0fa55h 0fa00h+55h=0fa55h ? fa 0f102h 00 0f101h ? 0a 35h jump to ? ~ ~ ~ ~ 35 0fa00h e3 36h ? 3f 0e30ah next ~ ~ ~ ~ address 0e30ah
preliminary mc80f0208/16/24 mar. 2005 ver 0.2 35 1625 adc [25h+x] y indexed indirect [dp]+y processes memory data as data, assigned by the data [dp+1][dp] of 16-bit pair memory paired by operand in direct page plus y- register data. adc, and, cmp, eor, lda, or, sbc, sta example; g=0, y=10 h 1725 adc [25h]+y absolute indirect [!abs] the program jumps to address specified by 16-bit absolute ad- dress. jmp example; g=0 1f25e0 jmp [!0c025h] 05 35h 0e005h ~ ~ ~ ~ 25 0fa00h e0 36h 16 0e005h data ~ ~ ~ ~ ? a + data + c a 25 + x(10) = 35h ? ? 05 25h 0e005h + y(10) ? ~ ~ ~ ~ 25 0fa00h e0 26h ? 17 0e015h data ~ ~ ~ ~ ? = 0e015h a + data + c a 25 0e025h jump to ~ ~ ~ ~ e0 0fa00h e7 0e026h ? 25 0e725h next ~ ~ ~ ~ 1f program memory ? address 0e30ah
mc80f0208/16/24 preliminary 36 mar. 2005 ver 0.2 9. i/o ports the mc80f0208/16/24 has six ports (r0, r1, r3, r4, r5 and r6). these ports pins may be multi plexed with an alternate func- tion for the peripheral features on the device. r3 port can drive maximum 20ma of high current in out put low state, so it can di- rectly drive led device. all pins have data di rection registers which can define these ports as output or input. a ?1? in the port direction register configure the corresponding port pin as output. conversely, write ?0? to the corresponding bit to specify it as input pin. for example, to use the even numbered bit of r0 as output ports and the odd num- bered bits as input ports, write ?55 h ? to address 0c1 h (r0 port direction register) during initial setting as shown in figure 9-1. all the port direction register s in the mc80f0208/16/24 have 0 written to them by reset function. on the other hand, its initial sta- tus is input. figure 9-1 example of port i/o assignment r0 and r0io register: r0 is an 8-bit cmos bidirectional i/o port (address 0c0 h ). each i/o pin can i ndependently used as an input or an output through th e r0io register (address 0c1 h ). the on-chip pull-up resistor can be connected to them in 1-bit units with a pull-up selection register 0 (pu0). r1 and r1io register: r1 is an 5-bit cmos bidirectional i/o port (address 0c2 h ). each i/o pin can independently used as an input or an output through the r1io register (address 0c3 h ). the on-chip pull-up resistor can be connected to them in 1-bit units with a pull-up selecti on register 1 (pu1). in addition, port r1 is multiplexed with various special features. the control register psr0 (address 0f8 h ) and psr1 (address 0f9 h ) controls the selection of alte rnate function. after reset, this value is ?0?, port may be used as normal i/o port. to use alternate function such as external interrupt, event counter input or timer clock output, writ e ?1? in the corresponding bit of psr0 or psr1. regardless of th e direction register r1io, psr0 or psr1 is selected to use as alternate functions, port pin can be used as a corresponding alternate features. i: input port write ?55 h ? to port r0 direction register 0 1 0 1 0 1 0 1 i o i o i o i o r0 data r1 data r0 direction r1 direction 0c0 h 0c1 h 0c2 h 0c3 h 76543210 bit 76543210 port o: output port port pin alternate function r10 r11 r12 r13 r15 int0 (external interrupt 0) int1 (external interrupt 1) int2 (external interrupt 2) buzo (square-wave output for buzzer) ec0 (event counter input to counter 0) r0 data register r0 address: 0c0 h reset value: 00 h r07 r06 r05 r04 r03 r02 r01 r00 port direction r0 direction register r0io address: 0c1 h reset value: 00 h 0: input 1: output input / output data r0 pull-up pu0 address: 0fc h reset value: 00 h selection register 0: disable 1: enable pull-up resister selection
preliminary mc80f0208/16/24 mar. 2005 ver 0.2 37 r3 and r3io register: r3 is an 4-bit cmos bidirectional i/o port (address 0c6 h ). each i/o pin can independently used as an input or an output through the r3io register (address 0c7 h ). in addition, port r3 is multiplexed with various special features. after reset, this value is ?0?, port may be used as normal i/o port. r4 and r4io register: r4 is an 8-bit cmos bidirectional i/o port (address 0c8 h ). each i/o pin can independently used as an input or an output through the r4io register (address 0c9 h ). the on-chip pull-up resistor can be connected to them in 1-bit units with a pull-up selection register 4 (pu4). in addition, port r4 is multiplexed with various special features. after reset, this value is ?0?, port may be used as normal i/o port. r1 data register r1 address: 0c2 h reset value: 00 h - - r15 - r13 r12 r11 r10 port direction r1 direction register r1io address: 0c3 h reset value: 00 h 0: input 1: output input / output data r1 pull-up pu1 address: 0fd h reset value: 00 h selection register 0: disable 1: enable pull-up resister selection - - - - - - psr0 address: 0f8 h reset value: 0-00 0000 b int2e port / int selection 0: r10, r11,r12, r50 1: int0, int1,int2, int3 - int0e int1e int3e pwm3o ec0e ec1e psr1 address: 0f9 h reset value: ---- -0-- b buzo r13/buzo selection 0: r13 port (turn off buzzer) 1: buzo port (turn on buzzer) - - - - - - - port / ec selection 0: r15, r51 1: ec0, ec1 port / pwm3 selection 0: r54 1: pwm3o/t3o port port pin alternate function r30 r31 r32 r33 - aclk1 (uart1 clock input) rxd1 (uart1 data input) txd1(uart1 data output) port pin alternate function r40 r41 r42 r43 r44 r45 r46 r47 - - sck (sio clock input/output) si (sio data input) so (serial1 data output) aclk0 (uart0 clock input) rxd0 (uart0 data input) txd0 (uart0 data output) r3 data register r3 address: 0c6 h reset value: 00 h - - - - r33 r32 r31 r30 port direction r3 direction register r3io address: 0c7 h reset value: 00 h 0: input 1: output input / output data - - - -
mc80f0208/16/24 preliminary 38 mar. 2005 ver 0.2 r5 and r5io register: r5 is an 3-bit cmos bidirectional i/o port (address 0ca h ). each i/o pin can independently used as an input or an output through the r5io register (address 0cb h ). in addition, port r5 is multiplex ed with various special features. the control register psr0 (address 0f8 h ) and psr1 (address 0f9 h ) controls the selection of alternate function. after reset, this value is ?0?, port may be used as normal i/o port. to use alternate function such as external interrupt, event counter input, timer clock output or pwm output, write ?1? in the corre- sponding bit of psr0 or psr1. rega rdless of the direction regis- ter r5io, psr0 or psr1 is selected to use as alternate functions, port pin can be used as a co rresponding altern ate features. r6 and r6io register: r6 is an 8-bit cmos bidirectional i/o port (address 0cc h ). each i/o pin can independently used as an input or an output through the r6io register (address 0cd h ). in addition, port r6 is multiplex ed with ad converter analog in- put an0~an7. r6io (address cd h ) controls the direction of the r6 pins, except when they are being used as an alog input channels. the user don?t have to keep the pins configured as inputs when using them as an- alog input channels, because the analog input mode is activated by the setting of adc enable b it of adcm register and adc port pin alternate function r50 r51 r54 int3 (external interrupt 3) ec1 (event counter input to counter 2) pwm3o (pwm3/t3o output) r4 data register r4 address: 0c8 h reset value: 00 h r47 r46 r45 r44 r43 r42 r41 r40 port direction r4 direction register r4io address: 0c9 h reset value: 00 h 0: input 1: output input / output data r4 pull-up pu4 address: 0fe h reset value: 00 h selection register 0: disable 1: enable pull-up resister selection port pin alternate function r60 r61 r62 r63 r64 r65 r66 r67 an0 (adc input channel 0) an1 (adc input channel 1) an2 (adc input channel 2) an3 (adc input channel 3) an4 (adc input channel 4) an5 (adc input channel 5) an6 (adc input channel 6) an7 (adc input channel 7) r5 data register r5 address: 0ca h reset value: ---00000 b - - - r54 - - r51 r50 port direction r5 direction register r5io address: 0cb h reset value: ---00000 b 0: input 1: output input / output data --- -- psr0 address: 0f8 h reset value: 0-00 0000 b int2e port / int selection 0: r10, r11, r12, r50 1: int0, int1, int2, int3 - int0e int1e int3e pwm3o ec0e ec1e port / ec selection 0: r15, r51 1: ec0, ec1 port / pwm3 selection 0: r54 1: pwm3o/t3o port
preliminary mc80f0208/16/24 mar. 2005 ver 0.2 39 channel selection . r6 data register r6 address: 0cc h reset value: 00 h r67 r66 r65 r64 r63r62r61r60 input / output data port direction r6 direction register r6io address: 0cd h reset value: 00 h 0: input 1: output
mc80f0208/16/24 preliminary 40 mar. 2005 ver 0.2 10. clock generator as shown in figure 10-1, the cl ock generator produces the basic clock pulses which provide the syst em clock to be supplied to the cpu and the peripheral hardware . it contains main-frequency clock oscillator. the system clock operation can be easily ob- tained by attaching a crystal or a ceramic resona tor between the x in and x out pin, respectively. the syst em clock can also be ob- tained from the external oscillator. in this case, it is necessary to input a external cl ock signal to the x in pin and open the x out pin. there are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip -flop, but minimum and maximum high and low times spec ified on the data sheet must be observed. to the peripheral block, the cl ock among the not-divided original clock, clocks divided by 1, 2 , 4,..., up to 4096 can be provided. peripheral clock is enabled or di sabled by stop instruction. the peripheral clock is contro lled by clock control register (ckctlr). see "11. basic in terval timer" on page 41 for details. figure 10-1 block diagram of clock generator internal prescaler 1 peripheral clock 2 4 8 16 128 256 512 1024 32 64 ps0 ps1 ps2 ps3 ps4 ps5 ps6 ps7 ps8 ps9 ps10 f ex (hz) ps0 ps3 ps2 ps4 ps1 ps10 ps9 ps5 ps6 ps7 4m frequency period 4m 1m 500k 250k 2m 125k 62.5k 250n 500n 1u 2u 4u 8u 16u 32u 64u 256u 128u 3.906k 7.183k 15.63k 31.25k ps8 2048 4096 ps12 ps11 1.953k 976 512u 1.024m main osc stop sleep f ex system clock ps12 ps11 x in clock pulse generator ( 2) stop osc circuit x out
preliminary mc80f0208/16/24 mar. 2005 ver 0.2 41 11. basic interval timer the mc80f0208/16/24 has one 8-bit ba sic interval timer that is free-run and can not stop. block diagram is shown in figure 11- 1. in addition, the basic interval timer generates the time base for watchdog timer counti ng. it also provides a basic interval tim- er interrupt (bitif). the 8-bit basic interval timer regi ster (bitr) is increased every internal count pulse which is di vided by prescaler. since prescal- er has divided ratio by 8 to 1024, the count rate is 1/8 to 1/1024 of the oscillator frequency. as the count overflow from ffh to 00h, this overflow causes the inte rrupt to be generated. the basic interval timer is controlled by the clock control register (ckctlr) shown in figure 10-2. when write "1" to bit btcl of ckctlr, bitr register is cleared to "0" and restart to co unt-up. the bit btcl becomes "0" after one machine cycle by hardware. if the stop instruction executed after writing "1" to bit rcwdt of ckctlr, it goes into the in ternal rc oscilla ted watchdog tim- er mode. in this mode, all of the block is halted except the internal rc oscillator, basic interval timer and watchdog timer. more detail informations are explaine d in power saving function. the bit wdton decides watchdog time r or the normal 7-bit timer. source clock can be selected by lower 3 bits of ckctlr. bitr and ckctlr are located at same address, and address 0f2 h is read as a bitr, and written to ckctlr. figure 11-1 block diagram of basic interval timer table 11-1 basic interval timer interrupt period mux basic interval bitr select input clock 3 basic interval timer source clock 8-bit up-counter bts[2:0] btcl 1024 512 256 128 64 32 16 8 to watchdog timer (wdtck) ckctlr clear overflow internal bus line clock control register [0f2 h ] [0f2 h ] bitif read x in pin prescaler timer interrupt internal rc osc rcwdt 1 0 rcwdt ckctlr [2:0] source clock interrupt (overflow) period (ms) @ f xin = 8mhz 000 001 010 011 100 101 110 111 f xin 8 f xin 16 f xin 32 f xin 64 f xin 128 f xin 256 f xin 512 f xin 1024 0.256 0.512 1.024 2.048 4.096 8.192 16.384 32.768
mc80f0208/16/24 preliminary 42 mar. 2005 ver 0.2 figure 11-2 bitr: basic in terval timer mode register example 1: interrupt request flag is generated every 8.192ms at 4mhz. : ldm ckctlr,#1bh set1 bite ei : example 2: interrupt request flag is ge nerated every 8.192ms at 8mhz. : ldm ckctlr,#1ch set1 bite ei : btcl 76543210 rcwdt - adrst bts1 basic interval timer source clock select 000: f xin 8 001: f xin 16 010: f xin 32 011: f xin 64 100: f xin 128 101: f xin 256 110: f xin 512 111: f xin 1024 clear bit 0: normal operation (free-run) 1: clear 8-bit counter (bitr) to ?0?. this bit becomes 0 automatically initial value: 0-01 0111 b address: 0f2 h after one machine cycle, and starts counting. ckctlr initial value: undefined address: 0f2 h bitr both register are in same address, when write, to be a ckctlr, when read, to be a bitr. caution: 8-bit free-run binary counter wdton bts0 bts2 btcl btcl 76543210 watchdog timer enable bit 0: operate as 7-bit timer see the section ?watchdog timer?. address trap reset selection 0: enable address fail reset 1: disable address fail reset 1: enable watchdog timer operation 0: disable internal rc watchdog timer 1: enable internal rc watchdog timer rc watchdog selection bit
preliminary mc80f0208/16/24 mar. 2005 ver 0.2 43 12. watchdog timer the watchdog timer rapidly dete cts the cpu malfunction such as endless looping caused by noise or the like, and resumes the cpu to the normal state. the watchdog timer signal for detecting mal- function can be selected either a reset cpu or a interrupt request. when the watchdog timer is not being used for malfunction de- tection, it can be used as a timer to generate an interrupt at fixed intervals. the watchdog timer has two types of clock source. the first type is an on-chip rc oscillator whic h does not require any external components. this rc oscillator is separate from the external os- cillator of the x in pin. it means that the watchdog timer will run, even if the clock on the x in pin of the device has been stopped, for example, by entering the stop mode. the other type is a prescaled system clock. the watchdog timer consists of 7-bit binary counter and the watchdog timer data register. wh en the value of 7-bit binary counter is equal to the lower 7 bits of wdtr, the interrupt re- quest flag is generate d. this can be used as watchdog timer inter- rupt or reset the cpu in accordance with the bit wdton. note: because the watchdog timer counter is enabled af- ter clearing basic interval time r, after the bit wdton set to "1", maximum error of timer is depend on prescaler ratio of basic interval timer. the 7-bit binary counter is cleared by setting wdtcl(bit7 of wdtr) and the wdtcl is cleared automatically afte r 1 machine cycle. the rc oscillated watchdog timer is activated by setting the bit rcwdt as shown below. ldm ckctlr,#3fh; enable the rc-osc wdt ldm wdtr,#0ffh ; set the wdt period ldm sscr, #5ah ;ready for stop mode stop ; enter the stop mode nop nop ; rc-osc wdt running : the rc-wdt oscillation period is vary with temperature, v dd and process variations from pa rt to part (approximately, 33~100us). the following equati on shows the rcwdt oscillat- ed watchdog timer time-out. t rcwdt =clk rcwdt 2 8 wdtr + (clk rcwdt 2 8) /2 where, clk rcwdt = 33~100us in addition, this watchdog timer can be used as a simple 7-bit tim- er by interrupt wdtif. the interval of watchdog timer interrupt is decided by basic inte rval timer. interval equation is as below. t wdt = (wdtr+1) interval of bit figure 12-1 block diagram of watchdog timer to reset cpu basic interval timer count enable watchdog 7-bit compare data comparator watchdog timer interrupt clear clear wdtif counter (7-bit) wdtcl ?0? ?1? wdton in ckctlr [0f2 h ] overflow watchdog timer register wdtr internal bus line 7 [0f4 h ] source
mc80f0208/16/24 preliminary 44 mar. 2005 ver 0.2 watchdog timer control figure 12-2 shows the watchdog timer control register. the watchdog timer is automatica lly disabled after reset. the cpu malfunction is detected during setting of the detection time, selecting of output, and cl earing of the binary counter. clearing the binary counter is repe ated within the detection time. if the malfunction occurs for any cause, the watchdog timer out- put will become active at the rising overflow from the binary counters unless the binary counter is cleared. at this time, when wdton=1, a reset is generate d, which drives the reset pin to low to reset the internal hard ware. when wdton=0, a watchdog timer interrupt (wdtif) is generated. the wdton bit is in reg- ister clkctlr. the watchdog timer temporarily stops counting in the stop mode, and when the stop mode is released, it automatically re- starts (continues counting). figure 12-2 wdtr: watchdog timer control register example: sets the watchdog timer detection time to 1 sec. at 4.194304mhz enable and disable watchdog watchdog timer is enabled by setting wdton (bit 4 in ckctlr) to ?1?. wdton is initialized to ?0? during reset and it should be set to ?1? to ope rate after reset is released. example: enables wa tchdog timer for reset : ldm ckctlr,#xxx1_xxxxb; wdton 1 : : the watchdog timer is disabled by clearing bit 4 (wdton) of ckctlr. the watchdog timer is ha lted in stop mode and re- starts automatically after stop mode is released. watchdog timer interrupt the watchdog timer can be also us ed as a simple 7-bit timer by clearing bit4 of ckctlr to ?0 ?. the interval of watchdog timer interrupt is decided by basic inte rval timer. interval equation is shown as below. t wdt = (wdtr+1) interval of bit the stack pointer (sp) should be initialized before using the watchdog timer output as an interrupt source. example: 7-bit timer interrupt set up. ldm ckctlr,#xxx0_xxxxb; wdton 0 ldm wdtr,#8fh ; wdtcl 1 : 76543210 wdtcl clear count flag 0: free-run count initial value: 0111 1111 b address: 0f4 h wdtr ww ww 1: when the wdtcl is set to ?1?, binary counter is cleared to ?0?. and the wdtcl becomes ?0? automatically after one machine cycle. counter count up again. 7-bit compare data wwww ldm ckctlr,#3fh ; select 1/1024 clock source , wdton 1, clear counter ldm wdtr,#08fh ldm wdtr,#08fh ; clear counter : : : : ldm wdtr,#08fh ; clear counter : : : : ldm wdtr,#08fh ; clear counter within wdt detection time within wdt detection time
preliminary mc80f0208/16/24 mar. 2005 ver 0.2 45 figure 12-3 watchdog timer timing if the watchdog timer output becomes active, a reset is generated, which drives the reset pin low to reset the internal hardware. the main clock oscillator also turns on when a watchdog timer reset is generated in sub clock mode. the wdtif bit of ifr register is set when watchdog timer inter- rupt is generated. (refer to figure 12-4) figure 12-4 ifr(interrupt flag register) 2 3 n source clock binary-counter wdtr wdtif interrupt wdtr ?1000_0011 b ? 1 0 match detect counter clear 1 2 30 bit overflow 3 wdt reset reset counter clear note1 : in case of using interrupts of watchdog timer and wa tch timer together, it is necessary to check ifr in interrupt service routine to find out which in terrupt is occurred, because the watchdog timer and watch timer is shared with interrupt vector address. t hese flag bits must be cleared by software after reading this register. r/w - initial value: --00 0000 b address: 0df h ifr - msb r/w uart0 tx interrupt occurred flag note3 uart0 rx interrupt occurred flag note3 lsb r/w r/w r/w r/w rx0iof tx0iof wtiof wdt interrupt occurred flag note1 wt interrupt occurred flag note1 uart1 tx interrupt occurred flag note2 uart1 rx interrupt occurred flag note2 rx1iof tx1iof wdtiof note2 : in case of using interrupts of uart1 tx and uart1 rx together, it is necessary to check ifr in interrupt service routine to find out which interrupt is occurred, because the uart1 tx and uart1 rx is shared with interrupt vector address. these flag bits must be cleared by software after reading this register. note3 : in case of using interrupts of uart0 tx and uart0 rx together, it is necessary to check ifr in interrupt service routine to find out which interrupt is occu rred, because the uart0 tx and uart0 rx is shared with interrupt vector address. these flag bits must be cleared by software after reading this register.
mc80f0208/16/24 preliminary 46 mar. 2005 ver 0.2 13. watch timer the watch timer generates interrupt for watch operation. the watch timer consists of the cloc k selector, 15-bit binary counter, interval selector and watch timer mode register. it is a multi-pur- pose timer. it is generall y used for watch design. the bit 0,1 of wtmr select the clock source of watch timer among f xin 2, f xin 2 7 and main-clock(f xin ). the f xin of main- clock is used usually for watch timer test, so generally it is not used for the clock source of watch timer. the f xin 2 7 of main- clock(4.194mhz) is used when th e single clock system is orga- nized. in f xin 2 7 clock source, if the cpu enters into stop mode, the main-clock is stopped and th en watch timer is also stopped. the watch timer counter can outpu t with period of max 1 seconds at sub-clock. the bit 2, 3, 4 of wtmr select the interrupt interval divide ratio selection of watc h timer among 16, 64, 256, 1024, 4096, 8192, 16384 or 32768. the wtif bit of ifr register is set when watch timer interrupt is generated. (refer to figure 12-4) figure 13-1 watch timer mode register figure 13-2 watch timer block diagram 7 6 5 4 3 2 1 0 initial value:0--0 0000 b address: 0f6 h wtmr (watch timer mode register) r/w r/w r/w r/w r/w wten (watch timer enable) 0: watch timer disable 1: watch timer enable watch timer interrupt interval selection w watch timer clock source selection 000: clock source 32768 001: clock source 16384 010: clock source 8192 011: clock source 4096 100: clock source 1024 101: clock source 256 110: clock source 64 111: clock source 16 00: - 01: f xin 128 10: f xin 11: f xin 2 -wtck1wtck0 wtin1 wtin0 wten wtin2 - mux f xin f xin 128 wtck[1:0] wtin[2:0] wten watch timer interrupt mux 1024 256 64 16 15-bit binary counter 32768 16384 8192 4096 interval selector clock source selector clear if wten=0 f xin 2 01 10 11
preliminary mc80f0208/16/24 mar. 2005 ver 0.2 47 14. timer/event counter the mc80f0208/16/24 has five timer/counter registers. each module can generate an interrupt to indicate that an event has oc- curred (i.e. timer match). timer 0 and timer 1 are can be used either two 8-bit timer/ counter or one 16-bit timer/co unter with combine them. also timer 2 and timer 3 are same. t imer 4 is 16-bit timer/counter. in the ?timer? function, the register is increased every internal clock input. thus, one can think of it as counting internal clock input. since a leas t clock consists of 2 a nd most clock consists of 2048 oscillator periods, the count ra te is 1/2 to 1/2048 of the os- cillator frequency. in the ?counter? function, the regi ster is increased in response to a 0-to-1 (rising edge) transition at its corresponding external input pin, ec0 or ec1. in addition the ?capture? function, the register is increased in re- sponse external or internal cl ock sources same with timer or counter function. when external clock edge input, the count reg- ister is captured into timer da ta register correspondingly. when external clock edge i nput, the count register is captured into cap- ture data register cdrx. timer 0 and timer 1 has four operating modes: "8-bit timer/ counter", "16-bit timer/counter", "8-bit capture" and "16-bit cap- ture" which are selected by bit in timer mode register tm0 and tm1 as shown in table 14-1, figure 14-1. timer 2 and timer 3 is shared with "pwm" function and "compare output" function. it has six operating modes: "8- bit timer/counter", "16-bit timer/counter", "8-bit capture", "16-bit capture", "8-bit co mpare output", and "10-bit pwm" which are selected by bit in timer mode register tm2 and tm3 as shown in table 14-2, figure 14-2. timer 4 has two operating modes: "16-bit timer/counter" and "16-bit capture" which are select ed by bit in timer mode register tm4 as shown intable 14-3, and figure 14-3. 16bit cap0 cap1 t0ck [2:0] t1ck [1:0] timer 0 timer 1 0 0 0 xxx xx 8-bit timer 8-bit timer 0 0 1 111 xx 8-bit event counter 8-bit capture 0 1 0 xxx xx 8-bit capture (internal clock) 8-bit timer 1 0 0 xxx 11 16-bit timer 1 0 0 111 11 16-bit event counter 1 1 1 xxx 11 16-bit capture (internal clock) table 14-1 operating modes of timer 0, 1 1. x means the value of ?0? or ?1? corresponds to user operation. 16bit cap2 cap3 pwm3e t2ck [2:0] t3ck [1:0] pwm3o timer 2 timer 3 0 0 0 0 xxx xx 0 8-bit timer 8-bit timer 0 0 1 0 111 xx 0 8-bit event counter 8-bit capture 0 1 0 0 xxx xx 1 8-bit capture (internal clock) 8-bit compare output 0 x 0 1 xxx xx 1 8-bit timer/counter 10-bit pwm 1 0 0 0 xxx 11 0 16-bit timer 1 0 0 0 111 11 0 16-bit event counter 1 1 1 0 xxx 11 0 16-bit capture (internal clock) table 14-2 operating modes of timer 2, 3
mc80f0208/16/24 preliminary 48 mar. 2005 ver 0.2 cap4 t4ck[2:0] timer 4 0 xxx 16-bit timer 1 xxx 16-bit capture (internal clock) table 14-3 operating modes of timer 4
preliminary mc80f0208/16/24 mar. 2005 ver 0.2 49 figure 14-1 tm0, tm1 registers btcl 76543210 16bit - t1cn initial value: -0-0 0000 b address: 0d2 h tm1 t1st t1ck0 t1ck1 - cap1 bit name bit position description 16bit tm1.6 0: 8-bit mode 1: 16-bit mode cap1 tm1.4 0: timer/counter mode 1: capture mode selection flag t1ck1 t1ck0 tm1.3 tm1.2 00: 8-bit timer, clock source is f xin 01: 8-bit timer, clock source is f xin 2 10: 8-bit timer, clock source is f xin 8 11: 8-bit timer, clock source is using the timer 0 clock t1cn tm1.1 0: timer count pause 1: timer count start t1st tm1.0 0: when cleared, stop the counting. 1: when set, timer 0 count register is cleared and start again. btcl 543210 - - t0cn initial value: --00 0000 b address: 0d0 h tm0 t0st t0ck0 t0ck1 cap0 t0ck2 bit name bit position description cap0 tm0.5 0: timer/counter mode 1: capture mode selection flag t0ck2 t0ck1 t0ck0 tm0.4 tm0.3 tm0.2 000: 8-bit timer, clock source is f xin 2 001: 8-bit timer, clock source is f xin 4 010: 8-bit timer, clock source is f xin 8 011: 8-bit timer, clock source is f xin 32 100: 8-bit timer, clock source is f xin 128 101: 8-bit timer, clock source is f xin 512 110: 8-bit timer, clock source is f xin 2048 111: ec0 (external clock) t0cn tm0.1 0: timer count pause 1: timer count start t0st tm0.0 0: when cleared, stop the counting. 1: when set, timer 0 count register is cleared and start again. 76543210 initial value: 0ff h address: 0d1 h tdr0 read: count value read write: compare data write r/w r/w r/w r/w r/w r/w r/w r/w - r/w - r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 76543210 initial value: 0ff h address: 0d3 h tdr1 r/w r/w r/w r/w r/w r/w r/w r/w
mc80f0208/16/24 preliminary 50 mar. 2005 ver 0.2 figure 14-2 tm2, tm3 registers btcl 76543210 16bit pol t3cn initial value: 00 h address: 0d8 h tm3 t3st t3ck0 t3ck1 pwm3e cap3 bit name bit position description pol tm3.7 0: pwm duty active low 1: pwm duty active high 16bit tm3.6 0: 8-bit mode 1: 16-bit mode pwm3e tm3.5 0: disable pwm 1: enable pwm cap3 tm3.4 0: timer/counter mode 1: capture mode selection flag t3ck1 t3ck0 tm3.3 tm3.2 00: 8-bit timer, clock source is f xin 01: 8-bit timer, clock source is f xin 4 10: 8-bit timer, clock source is f xin 16 11: 8-bit timer, clock source is using the timer 2 clock t3cn tm3.1 0: timer count pause 1: timer count start t3st tm3.0 0: when cleared, stop the counting. 1: when set, timer 0 count register is cleared and start again. btcl 543210 - - t2cn initial value: --00 0000 b address: 0d6 h tm2 t2st t2ck0 t2ck1 cap2 t2ck2 bit name bit position description cap2 tm2.5 0: timer/counter mode 1: capture mode selection flag t2ck2 t2ck1 t2ck0 tm2.4 tm2.3 tm2.2 000: 8-bit timer, clock source is f xin 2 001: 8-bit timer, clock source is f xin 4 010: 8-bit timer, clock source is f xin 8 011: 8-bit timer, clock source is f xin 16 100: 8-bit timer, clock source is f xin 64 101: 8-bit timer, clock source is f xin 256 110: 8-bit timer, clock source is f xin 1024 111: ec1 (external clock) t2cn tm2.1 0: timer count pause 1: timer count start t2st tm2.0 0: when cleared, stop the counting. 1: when set, timer 0 count register is cleared and start again. 76543210 initial value: 0ff h address: 0d7 h tdr2 read: count value read write: compare data write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 76543210 initial value: 0ff h address: 0d9 h tdr3 r/w r/w r/w r/w r/w r/w r/w r/w
preliminary mc80f0208/16/24 mar. 2005 ver 0.2 51 figure 14-3 tm4 register 14.1 8-bit timer / counter mode the mc80f0208/16/24 has four 8- bit timer/counters, timer 0, timer 1, timer 2, timer 3. th e timer 0, timer 1 are shown in figure 14-4 and timer 2, timer 3 are shown in figure 14-5. the ?timer? or ?counter? function is selected by control registers tm0, tm1, tm2, tm3 as shown in figure 14-1. to use as an 8- bit timer/counter mode, bit ca p0, cap1, cap2, or cap3 of tmx should be cleared to ?0? an d 16bit of tm1 or tm3 should be cleared to "0"(figure 14-4). these timers have each 8-bit count register and data register. the count re gister is increased by every internal or external clock input. the internal clock has a prescaler divide ratio option of 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048 or external cloc k (selected by control bits txck0, txck1, txck2 of register tmx). btcl 543210 - - t4cn initial value: --00 0000 b address: 0dc h tm4 t4st t4ck0 t4ck1 cap4 t4ck2 bit name bit position description cap4 tm4.5 0: timer/counter mode 1: capture mode selection flag t4ck2 t4ck1 t4ck0 tm4.4 tm4.3 tm4.2 000: 8-bit timer, clock source is f xin 2 001: 8-bit timer, clock source is f xin 4 010: 8-bit timer, clock source is f xin 8 011: 8-bit timer, clock source is f xin 16 100: 8-bit timer, clock source is f xin 64 101: 8-bit timer, clock source is f xin 256 110: 8-bit timer, clock source is f xin 1024 111: 8-bit timer, clock source is f xin 2048 t4cn tm4.1 0: timer count pause 1: timer count start t4st tm4.0 0: when cleared, stop the counting. 1: when set, timer 0 count register is cleared and start again. 76543210 initial value: 0ff h address: 0dd h tdr4h r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 76543210 initial value: 0ff h address: 0de h tdr4l r/w r/w r/w r/w r/w r/w r/w r/w
mc80f0208/16/24 preliminary 52 mar. 2005 ver 0.2 figure 14-4 8-bit timer/counter 0, 1 ec0 pin 2 4 8 x in pin mux prescaler clear 0: stop 1: clear and start t0st t0ck[2:0] 111 000 001 010 t0cn mux t1if clear 0: stop 1: clear and start t1st t1ck[1:0] 11 00 01 timer 1 interrupt 1 2 8 tdr0 (8-bit) tdr1 (8-bit) t1 (8-bit) t0 (8-bit) comparator comparator timer 0 timer 1 btcl 76543210 - -t0cn initial value: --00 0000 b address: 0d0 h tm0 t0st t0ck0 t0ck1 cap0 t0ck2 -- xx x x x means don?t care 512 2048 011 100 101 110 t0if timer 0 interrupt t1cn 10 initial value: -0-0 0000 b address: 0d2 h tm1 x means don?t care 0x btcl 76543210 16bit -t1cnt1st t1ck0 t1ck1 - cap1 -0 xx x x - 0 edge detector 128 32
preliminary mc80f0208/16/24 mar. 2005 ver 0.2 53 figure 14-5 8-bit timer/counter 2, 3 ec1 pin 2 4 8 x in pin mux prescaler clear 0: stop 1: clear and start t2st t2ck[2:0] 111 000 001 010 t2cn mux t3if clear 0: stop 1: clear and start t3st t3ck[1:0] 11 00 01 timer 3 interrupt 1 4 16 tdr2 (8-bit) tdr3 (8-bit) t3 (8-bit) t2 (8-bit) comparator comparator timer 2 timer 3 btcl 76543210 - -t2cn initial value: --000000 b address: 0d6 h tm2 t2st t2ck0 t2ck1 cap2 t2ck2 -- xx x x x means don?t care 256 1024 011 100 101 110 t2if timer 2 interrupt t3cn 10 initial value: 00 h address: 0d8 h tm3 x means don?t care 0x btcl 76543210 16bit pol t3cn t3st t3ck0 t3ck1 pwm3e cap3 x0 x x x x 00 edge detector f/f r54/pwm3o/t3o 64 16
mc80f0208/16/24 preliminary 54 mar. 2005 ver 0.2 example 1: timer0 = 2ms 8-bit timer mode at 4mhz timer1 = 0.5ms 8-bit timer mode at 4mhz timer2 = 1ms 8-bit timer mode at 4mhz timer3 = 1ms 8-bit timer mode at 4mhz ldm tdr0,#249 ldm tdr1,#249 ldm tdr2,#249 ldm tdr3,#249 ldm tm0,#0000_1111b ldm tm1,#0000_1011b ldm tm2,#0000_1111b ldm tm3,#0000_1011b set1 t0e set1 t1e set1 t2e set1 t3e ei example 2: timer0 = 8-bit event counter mode timer1 = 0.5ms 8-bit timer mode at 4mhz timer2 = 8-bit event counter mode timer3 = 1ms 8-bit timer mode at 4mhz ldm tdr0,#249 ldm tdr1,#249 ldm tdr2,#249 ldm tdr3,#249 ldm tm0,#0001_1111b ldm tm1,#0000_1011b ldm tm2,#0001_1111b ldm tm3,#0000_1011b set1 t0e set1 t1e set1 t2e set1 t3e ei these timers have each 8-bit count register and data register. the count register is incr eased by every internal or external clock in- put. the internal clock has a prescal er divide ratio option of 2, 4, 8, 32, 128, 512, 2048 selected by control bits t0ck[2:0] of reg- ister tm0 or 1, 2, 8 selected by control bits t1ck[1:0] of register tm1, or 2, 4, 8, 16, 64, 256, 1024 selected by control bits t2ck[2:0] of register tm2, or 1, 4, 16 selected by control bits t3ck[1:0] of register tm3. in th e timer 0, timer register t0 in- creases from 00 h until it matches tdr0 and then reset to 00 h . the match output of timer 0 gene rates timer 0 interrupt (latched in t0if bit). in counter function, the counter is increased every 0-to-1(1-to-0) (rising & falling edge) transition of ec0 pin. in order to use counter function, the bit ec0 of the port selection regis- ter(psr0.4) is set to "1". the ti mer 0 can be used as a counter by pin ec0 input, but timer 1 can not. likewise, in order to use timer2 as counter function, the bit ec1 of the port selection register(psr0.5) is set to "1". the timer 2 can be used as a counter by pin ec1 input , but timer 3 can not. 14.1.1 8-bit timer mode in the timer mode, the internal clock is used for counting up. thus, you can think of it as c ounting internal clock input. the contents of tdr n are compared with the contents of up-counter, t n . if match is found, a timer n interrupt (t n if) is generated and the up-counter is cleared to 0. counting up is resumed after the up-counter is cleared. as the value of tdr n is changeable by software, time interval is set as you want . figure 14-6 timer mode timing chart 0 n-2 2 0 n 3 n-1 n source clock up-counter tdr1 t1if interrupt start count 1 23 1 4 match detect counter clear ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
preliminary mc80f0208/16/24 mar. 2005 ver 0.2 55 figure 14-7 timer count example 14.1.2 8-bit event counter mode in this mode, counting up is star ted by an external trigger. this trigger means rising edge of the ec0 or ec1 pin input. source clock is used as an internal cloc k selected with timer mode regis- ter tm0 or tm2. the contents of timer data register tdr n (n = 0,1,2,3) are compared with the contents of the up-counter t n . if a match is found, an timer interrupt request flag t n if is generated, and the counter is cleared to ?0?. the counter is restart and count up continuously by every falling edge of the ec0 or ec1 pin in- put. the maximum frequency applied to the ec0 or ec1 pin is f xin /2 [hz]. in order to use event counter functi on, the bit 4, 5 of the port se- lection register psr0(address 0f8 h ) is required to be set to ?1?. after reset, the value of timer data register tdr n is initialized to "0", the interval period of timer is calculated as below equation. figure 14-8 event counter mode timing chart ~ ~ timer 0 (t0if) interrupt tdr0 time occur interrupt occur interrupt occur interrupt interrupt period up-count ~ ~ ~ ~ 0 1 2 3 4 5 6 7a 7c count pulse = 8 s x (124+1) 7b match example: make 1ms interrupt using by timer0 at 4mhz ldm tm0,#0fh ; divide by 32 ldm tdr0,#124 ; 8us x (124+1)= 1ms set1 t0e ; enable timer 0 interrupt ei ; enable master interrupt period when tdr0 = 124 d = 7c h f xin = 4 mhz interrupt period = 4 10 6 hz 1 32 (124+1) = 1 ms tm0 = 0000 1111 b (8-bit timer mode, prescaler divide ratio = 32) 8 s (tdr0 = t0) 7c 0 period (sec) 1 f xin ---------- - 2 divide ratio (tdrn+1) = 0 1 2 1 0 n 2 ~ ~ ~ ~ ~ ~ n-1 n ~ ~ ~ ~ ~ ~ ecn pin input up-counter tdr1 t1if interrupt start count
mc80f0208/16/24 preliminary 56 mar. 2005 ver 0.2 figure 14-9 count operation of timer / event counter timer 1 (t1if) interrupt tdr1 time occur interrupt occur interrupt stop clear & start disable enable start & stop t1st t1cn control count up-co u nt ~ ~ ~ ~ t1st = 0 t1st = 1 t1cn = 0 t1cn = 1
preliminary mc80f0208/16/24 mar. 2005 ver 0.2 57 14.2 16-bit timer / counter mode the timer register is being run with all 16 bits. a 16-bit timer/ counter register t0, t1 are incremented from 0000 h until it matches tdr0, tdr1 and then resets to 0000 h . the match out- put generates ti mer 0 interrupt. the clock source of the timer 0 is selected either internal or ex- ternal clock by bit t0ck[2:0 ]. in 16-bit mode, the bits t1ck[1:0] and 16bit of tm1 should be set to "1" respectively as shown in figure 14-10. likewise, a 16-bit timer/counter re gister t2, t3 are incremented from 0000 h until it matches tdr2, tdr3 and then resets to 0000 h . the match output genera tes timer 2 interrupt. the clock source of the timer 2 is selected either internal or ex- ternal clock by bit t2ck[2:0 ]. in 16-bit mode, the bits t3ck[1:0] and 16bit of tm3 shoul d be set to "1" respectively as shown in figure 14-11. even if the timer 0 (including time r 1) is used as a 16-bit timer, the timer 2 and timer 3 can still be used as either two 8-bit timer or one 16-bit timer by setting the tm2. reversely, even if the timer 2 (including timer 3) is us ed as a 16-bit timer, the timer 0 and timer 1 can still be used as 8-bit time r independently. a 16-bit timer/counter 4 register t4h, t4l are increased from 0000 h until it matches tdr4h, td r4l and then resets to 0000 h . the match output generates time r 4 interrupt. timer/counter 4 is 16 bit mode as shown in figure 14-12. figure 14-10 16-bit time r/counter for timer 0, 1 clear 0: stop 1: clear and start t0st t0cn tdr1 + tdr0 comparator timer 0 + timer 1 timer 0 (16-bit) higher byte lower byte (16-bit) compare data t1 + t0 (16-bit) (not timer 1 interrupt) edge btcl 76543210 - -t0cn initial value: --00 0000 b address: 0d0 h tm0 t0st t0ck0 t0ck1 cap0 t0ck2 -- xx x x x means don?t care initial value: -0-0 0000 b address: 0d2 h tm1 x means don?t care 0x btcl 76543210 16bit - t1cn t1st t1ck0 t1ck1 - cap1 -1 xx 1 1 -0 ec0 pin 2 4 8 x in pin mux prescaler t0ck[2:0] 111 000 001 010 512 2048 011 100 101 110 detector t0if timer 0 interrupt 128 32
mc80f0208/16/24 preliminary 58 mar. 2005 ver 0.2 figure 14-11 16-bit time r/counter for timer 2, 3 14.3 8-bit compare output (16-bit) the mc80f0208/16/24 has a function of timer compare output. to pulse out, the timer match can goes to port pin( t3o) as shown in figure 14-5 . thus, pulse out is generated by the timer match. these operation is implemente d to pin, pwm3o/t3o. in this mode, the bit pwm3o/t3o of r5 port selection register0 (psr0.7) should be set to "1 ", and the bit pwm3e of timer3 mode register (tm3) should be set to "0". this pin output the sig- nal having a 50 : 50 duty square wave, and output frequency is same as below equation. clear 0: stop 1: clear and start t2st t2cn tdr3 + tdr2 comparator timer 2 + timer 3 timer 2 (16-bit) higher byte lower byte (16-bit) compare data t3 + t2 (16-bit) (not timer 3 interrupt) edge btcl 76543210 - -t2cn initial value: --000000 b address: 0d6 h tm2 t2st t2ck0 t2ck1 cap2 t2ck2 -- xx x x x means don?t care initial value: 00 h address: 0d8 h tm3 x means don?t care 0 x btcl 76543210 16bit pol t3cn t3st t3ck0 t3ck1 pwm3e cap3 x1 x x 1 1 00 ec1 pin 2 4 8 x in pin mux prescaler t2ck[2:0] 111 000 001 010 256 1024 011 100 101 110 detector t2if timer 2 interrupt 64 16 f comp oscillation frequency 2 prescaler value tdr 1 ) + ( --------------------------------------------------------------------------------- =
preliminary mc80f0208/16/24 mar. 2005 ver 0.2 59 figure 14-12 timer 4 for only 16 bit mode 14.4 8-bit capture mode the timer 0 capture mode is set by bit cap0 of timer mode reg- ister tm0 (bit cap1 of timer m ode register tm1 for timer 1) as shown in figure 14-13. likewise, th e timer 2 capture mode is set by bit cap2 of timer mode re gister tm2 (bit cap3 of timer mode register tm3 for timer 3) as shown in figure 14-14. the timer/counter register is in creased in response internal or external input. this counting func tion is same with normal timer mode, and timer interrupt is generated when timer register t0 (t1, t2, t3) increases and matches tdr0 (tdr1, tdr2, tdr3). this timer interrupt in capture m ode is very useful when the pulse width of captured signal is more wider than the maximum period of timer. for example, in figure 14-16, the pulse width of captured signal is wider than the timer data value (ff h ) over 2 times. when ex- ternal interrupt is occurre d, the captured value (13 h ) is more little than wanted value. it can be obtained correct value by counting the number of timer overflow occurrence. timer/counter still does the above, but with the added feature that a edge transition at external input intx pin causes the current value in the timer x register (t0, t1,t2,t3), to be captured into registers cdrx (cdr0, cdr1, cd r2, cdr3), respectively. af- ter captured, timer x register is cleared and restarts by hardware. it has three transition modes: "fal ling edge", "rising edge", "both edge" which are selected by in terrupt edge selection register ieds. refer to ?19.5 external in terrupt? on page 92. in addition, the transition at int n pin generate an interrupt. note: the cdrn and tdrn are in same address.in the capture mode, reading operation is read the cdrn, not tdrn because path is opened to the cdrn. clear 0: stop 1: clear and start t4st t4cn tdr4h + tdr4l comparator higher byte lower byte (16-bit) compare data t4h + t4l (16-bit) initial value: 00 h address: 0dc h tm4 x means don?t care btcl 76543210 - - t4cn t4st t4ck0 t4ck1 cap4 t4ck2 xx x x x x 0 x 2 4 8 x in pin mux prescaler t4ck[2:0] 111 000 001 010 256 1024 011 100 101 110 t4if timer 4 interrupt 2048 64 16
mc80f0208/16/24 preliminary 60 mar. 2005 ver 0.2 figure 14-13 8-bit capture mode for timer 0, 1 int0if 0: stop 1: clear and start t0st int0 interrupt t0cn cdr0 (8-bit) t0 (8-bit) ?01? ?10? ?11? capture ieds[1:0] ec0 pin 2 4 8 x in pin mux prescaler t0ck[2:0] 111 000 001 010 mux t1ck[1:0] 11 00 01 1 2 8 512 2048 011 100 101 110 10 int0 pin int1if 0: stop 1: clear and start t1st int1 interrupt t1cn cdr1 (8-bit) t1 (8-bit) ?01? ?10? ?11? capture ieds[3:2] int1 pin btcl 76543210 - -t0cn initial value: --00 0000 b address: 0d0 h tm0 t0st t0ck0 t0ck1 cap0 t0ck2 -- xx x x x means don?t care initial value: -0-0 0000 b address: 0d2 h tm1 x means don?t care 1x btcl 76543210 16bit -t1cnt1st t1ck0 t1ck1 - cap1 -0 xx x x -1 edge detector clear clear 128 32
preliminary mc80f0208/16/24 mar. 2005 ver 0.2 61 figure 14-14 8-bit capture mode for timer 2, 3 int2if 0: stop 1: clear and start t2st int2 interrupt t2cn cdr2 (8-bit) t2 (8-bit) ?01? ?10? ?11? capture ieds[5:4] ec1 pin 2 4 8 x in pin mux prescaler t2ck[2:0] 111 000 001 010 mux t3ck[1:0] 11 00 01 1 4 16 256 1024 011 100 101 110 10 int2 pin int3if 0: stop 1: clear and start t3st int3 interrupt t3cn cdr3 (8-bit) t3 (8-bit) ?01? ?10? ?11? capture ieds[7:6] int3 pin btcl 76543210 - -t2cn initial value: --00 0000 b address: 0d6 h tm2 t2st t2ck0 t2ck1 cap2 t2ck2 -- xx x x x means don?t care initial value: 00 h address: 0d8 h tm3 x means don?t care 1x btcl 76543210 16bit pol t3cn t3st t3ck0 t3ck1 pwm3e cap3 x0 x x x x 01 edge detector clear clear 64 16
mc80f0208/16/24 preliminary 62 mar. 2005 ver 0.2 figure 14-15 input capture operation of timer 0 capture mode figure 14-16 excess timer overflow in capture mode ~ ~ ext. int0 pin interrupt request t0 time up - coun t ~ ~ ~ ~ 0 1 2 3 4 5 6 7 8 9 n n-1 capture ( timer stop ) clear & start interrupt interval period delay ( int0if ) ext. int0 pin interrupt request ( int0if ) this value is loaded to cdr0 20ns 5ns interrupt interval period=01 h +ff h +01 h +ff h +01 h +13 h =214 h ff h ff h ext. int0 pin interrupt request ( int0if ) 00 h 00 h interrupt request ( t0if ) t0 13 h
preliminary mc80f0208/16/24 mar. 2005 ver 0.2 63 14.5 16-bit capture mode 16-bit capture mode is the same as 8-bit capture, except that the timer register is bei ng run will 16 bits. the clock source of the timer 0 is selected either internal or external clock by bit t0ck[2:0]. in 16-bit mode, the bits t1ck1, t1ck0, cap1 and 16bit of tm1 should be set to "1 " respectively as shown in fig- ure 14-17. the clock source of the timer 2 is selected either internal or ex- ternal clock by bit t2ck[2:0]. in 16-bit mode, the bits t3ck1,t3ck0, cap3 and 16bit of tm3 should be set to "1" re- spectively as shown in figure 14-18. the clock source of the timer 4 is selected either internal or ex- ternal clock by bit t4ck[2:0] as shown in figure 14-18. figure 14-17 16-bit capture mode of timer 0, 1 0: stop 1: clear and start t0st t0cn capture cdr1 + cdr0 higher byte lower byte (16-bit) capture data tdr1 + tdr0 (16-bit) int0if int0 interrupt ?01? ?10? ?11? ieds[1:0] ec0 pin 2 4 8 x in pin mux prescaler t0ck[2:0] 111 000 001 010 32 128 512 2048 011 100 101 110 int0 pin btcl 76543210 - -t0cn initial value: --00 0000 b address: 0d0 h tm0 t0st t0ck0 t0ck1 cap0 t0ck2 -- xx x x x means don?t care initial value: -0-0 0000 b address: 0d2 h tm1 x means don?t care 1x btcl 76543210 16bit -t1cnt1st t1ck0 t1ck1 - cap1 -1 xx 1 1 - 1 edge detector clear
mc80f0208/16/24 preliminary 64 mar. 2005 ver 0.2 figure 14-18 16-bit capture mode of timer 2, 3 0: stop 1: clear and start t2st t2cn capture cdr3 + cdr2 higher byte lower byte (16-bit) capture data tdr3 + tdr2 (16-bit) int2if int2 interrupt ?01? ?10? ?11? ieds[5:4] ec1 pin 2 4 8 x in pin mux prescaler t2ck[2:0] 111 000 001 010 16 64 256 1024 011 100 101 110 int2 pin btcl 76543210 - -t2cn initial value: --000000 b address: 0d6 h tm2 t2st t2ck0 t2ck1 cap2 t2ck2 -- xx x x x means don?t care initial value: 00 h address: 0d8 h tm3 x means don?t care 1x btcl 76543210 16bit pol t3cn t3st t3ck0 t3ck1 pwm3e cap3 x1 x x 1 1 0 1 edge detector clear
preliminary mc80f0208/16/24 mar. 2005 ver 0.2 65 figure 14-19 16-bit capture mode of timer 4 example 1: timer0 = 16-bit time r mode, 0.5s at 4mhz ldm tm0,#0000_1111b;8us ldm tm1,#0100_1100b;16bit mode ldm tdr0,#<62499 ;8us x 62500 ldm tdr1,#>62499 ;=0.5s set1 t0e ei : : example 2: timer0 = 16-bit event counter mode ldm psr0,#0001_0000b;ec0 set ldm tm0,#0001_1111b;countermode ldm tm1,#0100_1100b;16bit mode ldm tdr0,#<0ffh ; ldm tdr1,#>0ffh ; set1 t0e ei : : example 3: timer0 = 16-bit capture mode ldm psr0,#0000_0001b;int0 set ldm tm0,#0010_1111b;capturemode ldm tm1,#0100_1100b;16bit mode ldm tdr0,#<0ffh ; ldm tdr1,#>0ffh ; ldm ieds,#01h;falling edge set1 t0e ei : : 0: stop 1: clear and start t4st t4cn capture cdr4h + cdr4l higher byte lower byte (16-bit) capture data tdr4h + tdr4l (16-bit) int3if int3 interrupt ?01? ?10? ?11? ieds[1:0] int3 pin clear initial value: 00 h address: 0dc h tm4 x means don?t care btcl 76543210 - -t4cnt4st t4ck0 t4ck1 cap4 t4ck2 xx x x x x 1x 2 4 8 x in pin mux prescaler t4ck[2:0] 111 000 001 010 16 64 256 1024 011 100 101 110 2048
mc80f0208/16/24 preliminary 66 mar. 2005 ver 0.2 14.6 pwm mode the mc80f0208/16/24 has a high speed pwm (pulse width modulation) functions whic h shared with timer3. in pwm mode, pin r54/pwm3o outputs up to a 10-bit resolu- tion pwm output. this pin should be configured as a pwm out- put by setting "1" bit pwm3o in psr0 register. the period of the pwm3 output is determined by the t3ppr (t3 pwm period register) and t3pwhr[3:2] (bit3,2 of t3 pwm high register) and the duty of th e pwm output is determined by the t3pdr (t3 pwm duty regist er) and t3pwhr[1:0] (bit1,0 of t3 pwm high register). the user writes the lower 8-bit period value to the t3ppr and the higher 2-bit period value to th e t3pwhr[3:2]. and writes duty value to the t3pdr and the t3pwhr[1:0] same way. the t3pdr is configured as a double buffering for glitchless pwm output. in figure 14-20, the duty data is transferred from the master to the slave when the period data matche d to the count- ed value. (i.e. at the be ginning of next duty cycle) pwm3 period = [pwm3hr[3: 2]t3ppr] x source clock pwm3 duty = [pwm3hr[1:0]t3pdr] x source clock the relation of frequency and reso lution is in inverse proportion. table 14-4 shows the relation of pwm frequency vs. resolution. if it needed more higher frequency of pwm, it should be reduced resolution. the bit pol of tm3 decides the polarity of duty cycle. if the duty value is set same to the period value, the pwm output is determined by the bit pol (1: high, 0: low). and if the duty value is set to "00 h ", the pwm output is determined by the bit pol (1: low, 0: high). it can be changed duty value wh en the pwm output. however the changed duty value is output after the current period is over. and it can be maintained the duty value at present output when changed only period value shown as figure 14-22. as it were, the absolute duty time is not change d in varying frequency. but the changed period value must greater than the duty value. note: if changing the timer3 to pwm function, it should be stop the timer clock firstly, and then set period and duty reg- ister value. if user writes register values while timer is in op- eration, these register could be set with certain values. ex) sample program @4mhz 4us ldm tm3,#1010_1000b ; set clock & pwm3e ldm t3ppr,#199 ; period :800us=4usx(199+1) ldm t3pdr,#99 ; duty:400us=4usx(99+1) ldm pwm3hr,00h ldm tm3,#1010_1011b ; start timer3 resolution frequency t3ck[1:0] = 00(250ns) t3ck[1:0] = 01(1us) t3ck[1:0] = 10(4us) 10-bit 3.9khz 1.95khz 0.97khz 9-bit 7.8khz 3.90khz 1.95khz 8-bit 15.6khz 7.81khz 3.90khz 7-bit 31.2khz 15.6khz 7.8khz table 14-4 pwm frequency vs. resolution at 4mhz
preliminary mc80f0208/16/24 mar. 2005 ver 0.2 67 figure 14-20 pwm3 mode t3st 0 : stop 1 : clear and start clear sq r pol pwm3o [psr0.7] period high duty high bit manipulation not available initial value: 00 h address: 0d8 h tm3 btcl 76543210 16bit pol t3cn t3st t3ck0 t3ck1 pwm3e cap3 x0 x x x x 10 r/w r/w r/w r/w r/w r/w r/w r/w initial value: ---- 0000 b address: 0db h t3pwhr x:the value "0" or "1" corresponding your operation. btcl 76543210 - - t3pwhr1 t3pwhr0 t3pwhr2 t3pwhr3 - - -- xx x x - - - - - -wwww initial value: 0ff h address: 0d9 h t3ppr btcl 76543210 wwwwwwww initial value: 00 h address: 0da h t3pdr btcl 76543210 x0 x x x x 1 0 r/w r/w r/w r/w r/w r/w r/w r/w x:the value "0" or "1" corresponding your operation. t3pdr(8-bit) t3pdr(8-bit) t3pwhr[1:0] slave master t3ppr(8-bit) t3pwhr[1:0] comparator t3cn 1 4 16 x in pin mux prescaler 00 01 10 t3ck[1:0] t2 clock source [t2ck] t3(8-bit) 2-bit comparator r53/pwm3o/t3o pin 11
mc80f0208/16/24 preliminary 68 mar. 2005 ver 0.2 figure 14-21 example of pwm at 4mhz figure 14-22 example of changing the period in absolute duty cycle (@8mhz) source t3 pwm3o ~ ~ ~ ~ ~ ~ 01 02 03 04 7e 7f 80 01 02 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ [pol=1] pwm3o [pol=0] duty cycle [ (1+7fh) x 250ns = 32us ] period cycle [ (3ffh+1) x 250ns = 256us, 3.9khz ] t3pwhr = 0ch t3ppr = ffh t3pdr = 7fh t3ck[1:0] = 00 ( xin ) t3pwhr3 t3pwhr2 t3pwhr1 t3pwhr0 t3ppr (8-bit) t3pdr (8-bit) period duty 1 1 ffh 00 7fh 00 clock pwm3e ~ ~ t3st ~ ~ t3cn ~ ~ 00 3ff source t3 pwm3o pol=1 duty cycle period cycle [ (1+0dh) x 2us = 28us, 35.5khz ] pwm3hr = 00h t3ppr = 0dh t3pdr = 04h t3ck[1:0] = 10 ( 2us ) 01 02 03 04 05 07 08 0a 0b 0c 0d 00 01 02 03 04 05 06 07 08 09 00 01 02 03 06 09 04 [ (04h+1) x 2us = 10us ] duty cycle [ (04h+1) x 2us = 10us ] period cycle [ (1+09h) x 2us = 20us, 50khz ] duty cycle [ (04h+1) x 2us = 10us ] write t3ppr to 09h clock 00
preliminary mc80f0208/16/24 mar. 2005 ver 0.2 69 15. analog to digital converter the analog-to-digital converter (a/d) allows conversion of an analog input signal to a correspondi ng 10-bit digital value. the a/ d module has sixteen analog input s, which are multiplexed into one sample and hold. the output of the sample and hold is the in- put into the converter, which ge nerates the result via successive approximation. the analog supply voltage is connected to av dd of sample & hold logic of a/d module. the av dd was separat- ed with v dd in order to minimize th e degradation of operation characteristic by power supply noise. the a/d module has three register s which are the control register adcm and a/d result register adcrh and adcrl. the ad- crh[7:6] is used as adc clock s ource selection bits too. the register adcm, shown in figure 15-4, controls the operation of the a/d converter module. the port pins can be configured as an- alog inputs or digital i/o. it is selected for the corresp onding channel to be converted by setting ads[3:0]. the a/d port is set to analog input port by aden and ads[3:0] regardless of port i/o direction register. the port unselected by ads[3: 0] operates as normal port. figure 15-1 a/d converter operation flow how to use a/d converter the processing of conversion is start when the start bit adst is set to ?1?. after one cycle, it is cleared by hardware. the register adcrh and adcrl contains the results of the a/d conversion. when the conversion is completed, the result is loaded into the adcrh and adcrl, the a/d conver sion status bit adsf is set to ?1?, and the a/d interrupt fl ag adcif is set. see figure 15-1 for operation flow. the block diagram of the a/d module is shown in figure 15-3. the a/d status bit ads f is set automatica lly when a/d conver- sion is completed, cleared when a/d conversion is in process. the conversion time takes 7 time s of conversion source clock. the period of actual a/d convers ion clock should be minimally 1 s figure 15-2 analog input pin connecting capacitor a/d converter cautions (1) input range of an0 to an7 the input voltage of an0 to an7 should be within the specifica- tion range. in particular, if a voltage above av dd or below av ss is input (even if within the ab solute maximum rating range), the conversion value for that channel can not be indeterminate. the conversion values of the other ch annels may also be affected. (2) noise countermeasures in order to maintain 10-bit resolu tion, attention mu st be paid to noise on pins av dd and an0 to an7. since the effect increases in proportion to the output impedance of the analog input source, it is recommended in some cases that a capacitor be connected ex- ternally as shown in figure 15-2 in order to reduce noise. the ca- pacitance is user-selectable and appropriately determined according to the target system. (3) pins an0/r60 to an7/r67 the analog input pins an0 to an7 also function as input/output port (port r6) pins. when a/d conversion is performed with any of pins an0 to an15 selected , be sure not to execute a port input instruction while conversion is in progres s, as this may re- duce the conversion resolution. also, if digital pulses ar e applied to a pin adjace nt to the pin in the process of a/d conversion, the expected a/d conversion value may not be obtainable due to c oupling noise. therefore, avoid ap- plying pulses to pins adjacent to the pin undergoing a/d conver- sion. adsf = 1 yes no enable a/d converter a/d input channel select conversion source clock select a/d start (adst = 1) nop read adcr an0~an7 analog input 0~1000pf user selectable
mc80f0208/16/24 preliminary 70 mar. 2005 ver 0.2 (4) av dd pin input impedance a series resistor string of approximately 5k ? is connected be- tween the av dd pin and the av ss pin. therefore, if the output impedance of the analog power source is high, this will result in parallel connection to the series resistor string between the av dd pin and the av ss pin, and there will be a large analog supply volt- age error. figure 15-3 a/d block diagram r60/an0 sample & hold r61/an1 r66/an6 r67/an7 successive approximation adcif adc result register adc interrupt mux resistor ladder circuit av dd av ss ads[4:2] circuit aden 8-bit adc adc result register adc8 01 2 3 8 9 0 1 adcrl (8-bit) 10-bit adcr adcrh 00 adcrl (8-bit) adcrh adcr (10-bit) 8 9 10-bit adcr 10-bit mode 8-bit mode 0 1
preliminary mc80f0208/16/24 mar. 2005 ver 0.2 71 figure 15-4 a/d converter control & result register btcl 76543210 aden adst a/d status bit analog input channel select initial value: 00-0 0001 b address: 0ef h adcm adsf a/d converter clock source devide ratio selection bit - r/w r/w r/w r/w r 000: channel 0 (an0) 001: channel 1 (an1) 010: channel 2 (an2) 011: channel 3 (an3) 100: channel 4 (an4) 101: channel 5 (an5) 110: channel 6 (an6) 0: a/d conversion is in progress 1: a/d conversion is completed a/d start bit setting this bit starts an a/d conversion. after one cycle, bit is cleared to ?0? by hardware. ads1 ads0 - ads2 adck 111: channel 7 (an7) a/d converter enable bit 0: a/d converter module turn off and current is not flow. 1: enable a/d converter initial value: undefined address: 0f1 h adcrl a/d conversion low data r/w r/w btcl 76543210 pssel1 adcrh - - adc8 - pssel0 initial value: 010- ---- b address: 0f0 h a/d conversion high data a/d conversion clock (f ps ) source selection btcl 76543210 rr ww rrrrrr rr adck pssel1 pssel0 ps clock selection 0 0 0 ps = f xin 4 00 1 ps = f xin 8 01 0 ps = f xin 16 01 1 ps = f xin 32 10 0 ps = f xin 8 10 1 ps = f xin 16 11 0 ps = f xin 32 11 1 ps = f xin 64 ps : conversion clock adc 8-bit mode select bit 0: 10-bit mode 1: 8-bit mode w 0: clock source f ps 4 1: clock source f ps 8 00: f xin 01: f xin 2 10: f xin 4 11: f xin 8
mc80f0208/16/24 preliminary 72 mar. 2005 ver 0.2 16. serial input/output (sio) the serial input/output is used to transmit/receive 8-bit data se- rially. the serial input/output(s io) module is a serial interface useful for communicating with ot her peripheral of microcontrol- ler devices. these peripheral devices may be serial eeproms, shift registers, display drivers, a/ d converters, etc. this sio is 8- bit clock synchronous type and consis ts of serial i/o data register, serial i/o mode register, clock se lection circuit, octal counter and control circuit as illustrated in figure 16-1. the so pin is de- signed to input and output. so the serial i/o(sio) can be operated with minimum two pin. pin r42/ sck, r43/si, and r44/so pins are controlled by the serial mode register. the contents of the serial i/o data register can be wr itten into or read out by software. the data in the serial data regi ster can be shifted synchronously with the transfer clock signal. figure 16-1 sio block diagram 4 16 x in pin prescaler mux sck[1:0] 00 01 10 11 sck pin sio shift input shift register sior clock clock octal serial communication interrupt sioif internal bus siosf counter sck[1:0] ?11? overflow not ?11? complete timer0 overflow si pin iosw so pin sout iosw control circuit ?0? ?1? pol 1 0 start siost clear sm0 (3-bit)
preliminary mc80f0208/16/24 mar. 2005 ver 0.2 73 serial i/o mode regist er(siom) controls seri al i/o function. ac- cording to sck1 and sck0, the in ternal clock or external clock can be selected. serial i/o data regist er(sior) is an 8-bit shift register. first lsb is send or is received. figure 16-2 sio control register 16.1 transmission/receiving timing the serial transmission is starte d by setting siost(bit1 of siom) to ?1?. after one cycle of sck, siost is cleared automatically to ?0?. at the default state of po l bit clear, the serial output data from 8-bit shift register is output at falling edge of sclk, and in- put data is latched at rising edge of sclk pin (refer to figure 16- 3). when transmission clock is c ounted 8 times, se rial i/o counter is cleared as ?0?. transmission clock is halted in ?h? state and se- rial i/o interrupt (sioif) occurred. btcl 76543210 iosw pol siost serial transmission status bit serial transmission clock selection initial value: 0000 0001 b address: 0e2 h siom siosf serial input pin selection bit 0: si pin selection 1: so pin selection r/w r/w r/w r/w r/w r 00: f xin 4 01: f xin 16 10: tmr0ov(timer0 overflow) 11: external clock 0: serial transmission is in progress 1: serial transmis sion is completed serial transmission start bit setting this bit starts an serial transmission. after one cycle, bit is cleared to ?0? by hardware. sck1 sck0 sm1 sm0 r/w serial transmission operation mode 00: normal port(r42,r43,r44) 01: sending mode(sck,r43,so) 10: receiving mode(sck,si,r44) 11: sending & receiving mode(sck,si,so) initial value: undefined address: 0e3 h sior btcl 76543210 r/w r/w r/w r/w r/w r/w r/w r/w sending data at sending mode receiving data at receiving mode serial clock polarity selection bit 0: data transmission at falling edge received data latch at rising edge 1: data transmission at rising edge received data latch at falling edge r/w
mc80f0208/16/24 preliminary 74 mar. 2005 ver 0.2 figure 16-3 serial i/o timing diagram at pol=0 figure 16-4 serial i/o timing diagram at pol=1 d1 d2 d3 d4 d6 d7 d0 d5 d1 d2 d3 d4 d6 d7 d0 d5 siost sck [r42] (pol=0) so [p44] si [r43] sioif (sio int. req) (iosw=0) d1 d2 d3 d4 d6 d7 d0 d5 ioswin [p44] (iosw=1) siosf (sio status) d1 d2 d3 d4 d6 d7 d0 d5 d1 d2 d3 d4 d6 d7 d0 d5 siost sck [r42] (pol=1) so [r44] si [r43] sioif (sio int. req) (iosw=0) d1 d2 d3 d4 d6 d7 d0 d5 ioswin [r44] (iosw=1) siosf (sio status)
preliminary mc80f0208/16/24 mar. 2005 ver 0.2 75 16.2 the method of serial i/o 1. select transmission/receiving mode. 2. in case of sending mode, write data to be send to sior. 3. set siost to ?1? to st art serial transmission. 4. the sio interrupt is generated at the completion of sio and sioif is set to ?1?. in sio interrupt service routine, correct transmission should be tested. 5. in case of receiving mode, the received data is acquired by reading the sior. note: when external clock is used, the frequency should be less than 1mhz and recommended duty is 50%. if both transmission mode is selected and transmission is per- formed simultaneously, error will be made. 16.3 the method to test correct transmission figure 16-5 serial io method to test transmission ldm sior,#0aah ;set tx data ldm siom,#0011_1100b ;set sio mode nop ldm siom,#0011_1110b ;sio start serial i/o interrupt service routine sioe = 0 write siom normal operation overrun error abnormal siosf 0 1 - sioe: interrupt enable register high ienh(bit3) - sioif: interrupt request flag register high irqh(bit3) sioif 0 1
mc80f0208/16/24 preliminary 76 mar. 2005 ver 0.2 17. universal asynchro nous receiver/transmitter (uart) 17.1 uart serial interface functions the universal asynchronous r eceiver/transmitter(uart) en- ables full-duplex operation wherein one byte of data after the start bit is transmitted and received. the on-chip baud rate generator dedicated to uart enables comm unications using a wide range of selectable baud rates. in addi tion, a baud rate can also be de- fined by dividing clocks input to the aclk pin. the uart driver consists of rxr, txr, asimr, asisr and brgcr register. clock asynchr onous serial i/o mode (uart) can be selected by asimr regist er. figure 17-1 shows a block di- agram of the uart driver. note: the uart1 control register asimr1,asisr1, brgcr1, rxr1 and txr1 are located at ee6h ~ ee9h address. these address must be accessed(read and writ- ten) by absolute addressing manipulation instruction. figure 17-1 uart block diagram (asisr) transmit shift register internal data bus txd pin rxd pin txe rxe aclk pin f xin /2 ~ f xin /2 7 (txr) transmit controller (parity addition) receive buffer register (rxr) receive shift register (rx) receive controller (parity check) baud rate generator 210 pe fe ove uartxif txxiof (uartx interrupt) rxxiof
preliminary mc80f0208/16/24 mar. 2005 ver 0.2 77 figure 17-2 baud rate generator block diagram figure 17-3 ifr : in terrupt flag register mux receive rxe tx_clock rx_clock txe send 5-bit counter decoder 5-bit counter match match (brgcr) - tps2 tps1 tps0 mdl3 mdl2 mdl1 mdl0 aclk pin f xin /2 ~ f xin /2 7 internal data bus 1/2 (divider) 1/2 (divider) note1 : in case of using interrupts of watchdog timer and watch timer together, it is necessary to check ifr in interrupt serv ice routine to find out which interrupt is occurred, because the watchdog timer and watch timer is shared with interrupt vector address. these flag bits must be cleared by software after reading this register. r/w - initial value: --00 0000 b address: 0df h ifr - msb r/w uart0 tx interrupt occurred flag note3 uart0 rx interrupt occurred flag note3 lsb r/w r/w r/w r/w rx0iof tx0iof wtiof wdt interrupt occurred flag note1 wt interrupt occurred flag note1 uart1 tx interrupt occurred flag note2 uart1 rx interrupt occurred flag note2 rx1iof tx1iof wdtiof note2 : in case of using interrupts of uart1 tx and uart1 rx together, it is necessary to check ifr in interrupt service routine to find out which interrupt is occurred, because the uart1 tx and uart1 rx is shared with interrupt vector address. these flag bits must be cleared by software after reading this register. note3 : in case of using interrupts of uart0 tx and uart0 rx together, it is necessary to check ifr in interrupt service routine to find out which interrupt is occurred, because the uart0 tx and uart0 rx is shared with interrupt vector address. these flag bits must be cleared by software after reading this register.
mc80f0208/16/24 preliminary 78 mar. 2005 ver 0.2 17.2 serial interface configuration the uart interface consists of the following hardware. transmit shift register (txr) this is the register for setting transmit data. data written to txr0 is transmitted as serial data. when the data length is set as 7 bit, bit 0 to 6 of the data written to tx0 are transferred as transmit da- ta. writing data to txr0 st arts the transmit operation. txr0 can be written by an 8 b it memory manipulation instruc- tion. it cannot be read. the reset input sets txr0 to 0ff h . note: do not write to txr during a transmit operation. the same address is assigned to txr and the receive buffer register (rxr). a read operation reads values from rxr. receive buffer register (rxr) this register is used to hold re ceive data. when one byte of data is received, one byte of new rece ive data is transferred from the receive shift register (rxsr). when the data length is set as 7 bits, receive data is sent to bits 0 to 6 of rxr0. in this case, the msb of rxr always becomes 0. rxr can be read by an 8 bit memo ry manipulation instruction. it cannot be written. the reset input sets rxr0 to 00 h . note: the same address is assigned to rxr and the transmit shift register (txr). during a write operation, val- ues are written to txr. receive shift register this register converts serial data input via the rxd pin to paral- leled data. when one byte of data is received at this register can- not be manipulated directly by a program. asynchronous serial interface mode register (asimr) this is an 8 bit register that c ontrols uart serial transfer opera- tion. asimr is set by a 1 bit or 8 bit memory manipulation in- truction. the reset input sets asimr to 0000_-00- b . table 17- 4 shows the format of asimr. note: do not switch the operation mode until the current serial transmit/receive operation has stopped. . figure 17-4 asynchronous serial inte rface mode register (asimr0) format item configuration register transmit shift register (txr) receive buffer register (rxr) receive shift register control register serial interface mode register (asimr) serial interface status register (asisr) baudrate generator co ntrol register (brgcr) table 17-1 serial interface configuration btcl 76543210 rxe0 txe0 isrm0 uart0 stop bit length for specification for transmit data bit initial value: 0000 -00- b address: 0e6 h asimr0 - r/w r/w r/w r/w r/w 0: 1 bit 1: 2 bit uart0 receive interrupt request is issued when an error occurs bit - sl0 ps01 ps00 r/w uart0 parity bit specification bit 00: no parity 01: zero parity always added during transmission. 10: odd parity 11: even parity uart0 tx/rx enable bit r/w 0: receive completion interrupt control when error occurs 1: receive completion interrupt request is not issued when an error occur no parity detection during reception (parity errors do not occur) 00: not used uart0 (r46, r47) 01: uart0 receive only mode(rxd, r47) 10: uart0 transmit only mode(r46, txd) 11: uart0 receive & transmit mode(rxd, txd)
preliminary mc80f0208/16/24 mar. 2005 ver 0.2 79 asynchronous serial interface status register0 (asisr) when a receive error occurs during uart mode, this register in- dicates the type of error. asis r can be read by an 8 bit memory manipulation instruction. the reset input sets asisr0 to ----- 000b. figure 17-5 shows the format of asisr. . figure 17-5 asynchronous serial interface status register (asisr) format btcl 76543210 - - fe0 uart0 frame error flag initial value: ---- -000 b address: 0e7 h asisr0 ove0 rrr 0: no frame error 1: framing error note1 (stop bit not detected) uart0 parity error flag - pe0 - - uart0 overrun error flag 0: no overrun error 1: overrun error note2 0: no parity error 1: parity error (transmit data parity not matched) note 1. even if a stop bit length is set to 2 bits by setting bit2(sl) in asimr, stop bit detection during a recive operation only applies to a stop bit length of 1bit. 2. be sure to read the contents of the receive buffer register(rxr) when an overrun error has occurred. until the contents of rxr are re ad, futher overrun errors will occur when receiving data. (next receive operation was completed before data was read from receive buffer register (rxr))
mc80f0208/16/24 preliminary 80 mar. 2005 ver 0.2 baud rate generator control register (brgcr) this register sets the serial clock for serial interface. brgcr is set by an 8 bit memory manipulation instruction. the reset in- put sets brgcr to -001_0000b. figure 17-6 shows the format of brgcr. . figure 17-6 baud rate generato r control register0(brgcr) format btcl 76543210 tps02 - mdl01 initial value: -001 0000 b address: 0e8 h brgcr0 mdl00 rrr mdl03mdl02 tps01 tps00 uart0 source clock selection for 5 bit count 000: aclk/r45 001: f xin / 2 010: f xin / 4 011: f xin / 8 100: f xin / 16 101: f xin / 32 110: f xin / 64 111: f xin / 128 uart0 input clock selection 0000: f sck / 16 0001: f sck / 17 0010: f sck / 18 0011: f sck / 19 0100: f sck / 20 0101: f sck / 21 0110: f sck / 22 0111: f sck / 23 1000: f sck / 24 1001: f sck / 25 1010: f sck / 26 1011: f sck / 27 1100: f sck / 28 1101: f sck / 29 1110: f sck / 30 1111: setting prohibited 1. f sck : source clock for 5 bit counter 2. n : value set via tps0 to tps2 ( 0 n 7 ) 3. k : source clock for 5 bit counter ( 0 k 14 ) remarks writing to brgcr0 during a communication operation may cause abnormal output from the baud rate generator and disable further communication operations. therefore, do not write to brgcr0 during a communication operation. caution
preliminary mc80f0208/16/24 mar. 2005 ver 0.2 81 17.3 communication operation the transmit operation is enabled when bit 7 (txe0) of the asyn- chronous serial interface mode regi ster (asimr) is set to 1. the transmit operation is started when transmit data is written to the transmit shift register (txr). the timing of the transmit comple- tion interrupt request is shown in figure 17-8. the receive operation is enabled when bit 6 (rxe0) of the asyn- chronous serial interface mode regi ster (asimr) is set to 1, and input via the rxd pin is sampled. the serial clock specified by asimr is used to sample the rxd pin. once reception of one data frame is completed, a r eceive completion interrupt request (int_rx0) occurs. even if an error has occurred, the receive data in which the error occurred is still transferred to rxr. when asimr bit 1 (isrm0) is cleared to 0 upon occurrence of an error, and int_rx0 occurs. when isrm bit is set to 1, int_rx0 does not occur in case of error occu rrence. figure 17-8 shows the tim- ing of the asynchronous serial in terface receive completion inter- rupt request. in case of using interrupts of uart0 tx and uart0 rx togeth- er, it is necessary to check ifr in interrupt service routine to find out which interrupt is occurr ed, because the uart0 tx and uart0 rx is shared with interrupt vector address. these flag bits must be cleared by softwa re after reading this register. in case of using interrupts of uart1 tx and uart1 rx togeth- er, it is necessary to check ifr in interrupt service routine to find out which interrupt is occurr ed, because the uart1 tx and uart1 rx is shared with interrupt vector address. these flag bits must be cleared by softwa re after reading this register. each processing step is determined by ifr as shown in figure 17- 7. figure 17-7 shared interrupt vector of uart tx0iof(tx1iof) tx0(tx1) interrupt uart0(uart1) interrupt request =0 =1 routine clear tx0iof(tx1iof) rx0iof(rx1iof) rx0(rx1) interrupt reti =0 =1 routine clear rx0iof(rx1iof)
mc80f0208/16/24 preliminary 82 mar. 2005 ver 0.2 figure 17-8 uart data format an d interrupt timing diagram d0 d1 txd tx d2 rxd d4 d3 d6 d5 d7 parity interrupt stop 1 data frame character bits 1 data frame consists of following bits. - start bit : 1 bit - character bits : 8 bits - parity bit : even parity, odd parity, zero parity, no parity - stop bit(s) : 1 bit or 2 bits rx interrupt start 1. stop bit length : 1 bit d0 d1 txd tx d2 rxd d4 d3 d6 d5 d7 parity interrupt stop 1 data frame character bits rx interrupt start 2. stop bit length : 2 bit d0 d1 txd tx d2 rxd d4 d3 d6 d5 d7 interrupt 1 data frame character bits rx interrupt start 3. stop bit length : 1 bit, no parity stop
preliminary mc80f0208/16/24 mar. 2005 ver 0.2 83 17.4 relationship between main clock and baud rate the transmit/receive clock that is used to generate the baud rate is obtained by dividing the main system clock. transmit/receive clock generation for baud rate is made by using main system clock which is divided. the baud rate generated from the main system clock is determined accordi ng to the following formula. figure 17-9 relationship between main clock and baud rate baud rate (bps) f xin =11.0592m f xin =10.0m f xin =8.0m f xin =6.0m f xin =4.0m f xin =2.0m brgcr err (%) brgcr err (%) brgcr err (%) brgcr err (%) brgcr err (%) brgcr err (%) 600 - - - - - - - - 7ah 0.16 6ah 0.16 1200 - - - - 7ah 0.16 74h 2.34 6ah 0.16 5ah 0.16 2400 72h 0.00 70h 1.73 6ah 0.16 64h 2.34 5ah 0.16 4ah 0.16 4800 62h 0.00 60h 1.73 5ah 0.16 54h 2.34 4ah 0.16 3ah 0.16 9600 52h 0.00 50h 1.73 4ah 0.16 44h 2.34 3ah 0.16 2ah 0.16 19200 42h 0.00 40h 1.73 3ah 0.16 34h 2.34 2ah 0.16 1ah 0.16 31250 36h 0.53 34h 0.00 30h 0.00 28h 0.00 20h 0.00 10h 0.00 38400 32h 0.00 30h 1.73 2ah 0.16 24h 2.34 1ah 0.16 - - 57600 28h 0.00 26h 1.35 21h 2.11 1ah 0.16 11h 2.12 - - 76800 22h 0.00 20h 1.73 1ah 0.16 14h 2.34 ---- 115200 18h 0.00 16h 1.36 11h 2.12 - - ---- 2. f sck : source clock for 5 bit counter 3. n : value set via tps00 to tps02 ( 0 n 7 ) 4. k : source clock for 5 bit counter ( 0 k 14 ) remarks 1. f xin : main system clock os cillation frequency when aclk is selected as the source clock of the 5-bit counter, substitute the input clock frequency to aclk pin for in the above expression. baud rate = f xin / ( 2 n+1 (k+16) )
mc80f0208/16/24 preliminary 84 mar. 2005 ver 0.2 18. buzzer function the buzzer driver block consists of 6-bit binary counter, buzzer register buzr, and clock source selector. it generates square- wave which has very wide ra nge frequency (488hz ~ 250khz at f xin = 4mhz) by user software. a 50% duty pulse can be output to r13/buzo pin to use for pi- ezo-electric buzzer drive. pin r 13 is assigned for output port of buzzer driver by setting the bit 2 of psr1(address 0f9 h ) to ?1?. for psr1 register, refer to figure 18-2. example: 5khz out put at 4mhz. ldm buzr,#0011_0001b ldm psr1,#xxxx_x1xxb x means don?t care the bit 0 to 5 of buzr determ ines output frequency for buzzer driving. equation of frequency calc ulation is shown below. f buz : buzzer frequency f xin : oscillator frequency divide ratio: prescaler divide ratio by buck[1:0] bur: lower 6-bit value of buzr. buzzer period value. the frequency of output signal is c ontrolled by the buzzer control register buzr. the bit 0 to bit 5 of buzr determine output fre- quency for buzzer driving. figure 18-1 block diagram of buzzer driver figure 18-2 buzzer register & psr1 f buz f xin 2 divideratio bur 1 + () --------------------------------------------------------------------------- - = prescaler 8 32 16 64 bur r13/buzo pin psr1 internal bus line r13 port data x in pin 2 6 [0e0 h ] [0f9 h ] 0 1 f/f comparator compare data 6-bit binary mux 00 01 10 11 port selection register 1 mux buzo counter bur[5:0] buzr address: 0e0 h reset value: 0ff h wwww ww source clock select 00: f xin 8 01: f xin 16 10: f xin 32 11: f xin 64 buzzer period data ww buck1 buck0 psr1 address: 0f9 h reset value: ---- -0-- b buzo r13/buzo selection 0: r13 port (turn off buzzer) 1: buzo port (turn on buzzer) - - - - - - -
preliminary mc80f0208/16/24 mar. 2005 ver 0.2 85 the 6-bit counter is cleared and starts the counting by writing sig- nal at buzr register. it is incremental from 00 h until it matches 6-bit bur value. when main-frequency is 4mhz, buzzer frequency is shown as below table 18-1. bur [5:0] bur[7:6] bur [5:0] bur[7:6] 00 01 10 11 00 01 10 11 00 01 02 03 04 05 06 07 250.000 125.000 83.333 62.500 50.000 41.667 35.714 31.250 125.000 62.500 41.667 31.250 25.000 20.833 17.857 15.625 62.500 31.250 20.833 15.625 12.500 10.417 8.929 7.813 31.250 15.625 10.417 7.813 6.250 5.208 4.464 3.906 20 21 22 23 24 25 26 27 7.576 7.353 7.143 6.944 6.757 6.579 6.410 6.250 3.788 3.676 3.571 3.472 3.378 3.289 3.205 3.125 1.894 1.838 1.786 1.736 1.689 1.645 1.603 1.563 0.947 0.919 0.893 0.868 0.845 0.822 0.801 0.781 08 09 0a 0b 0c 0d 0e 0f 27.778 25.000 22.727 20.833 19.231 17.857 16.667 15.625 13.889 12.500 11.364 10.417 9.615 8.929 8.333 7.813 6.944 6.250 5.682 5.208 4.808 4.464 4.167 3.906 3.472 3.125 2.841 2.604 2.404 2.232 2.083 1.953 28 29 2a 2b 2c 2d 2e 2f 6.098 5.952 5.814 5.682 5.556 5.435 5.319 5.208 3.049 2.976 2.907 2.841 2.778 2.717 2.660 2.604 1.524 1.488 1.453 1.420 1.389 1.359 1.330 1.302 0.762 0.744 0.727 0.710 0.694 0.679 0.665 0.651 10 11 12 13 14 15 16 17 14.706 13.889 13.158 12.500 11.905 11.364 10.870 10.417 7.353 6.944 6.579 6.250 5.952 5.682 5.435 5.208 3.676 3.472 3.289 3.125 2.976 2.841 2.717 2.604 1.838 1.736 1.645 1.563 1.488 1.420 1.359 1.302 30 31 32 33 34 35 36 37 5.102 5.000 4.902 4.808 4.717 4.630 4.545 4.464 2.551 2.500 2.451 2.404 2.358 2.315 2.273 2.232 1.276 1.250 1.225 1.202 1.179 1.157 1.136 1.116 0.638 0.625 0.613 0.601 0.590 0.579 0.568 0.558 18 19 1a 1b 1c 1d 1e 1f 10.000 9.615 9.259 8.929 8.621 8.333 8.065 7.813 5.000 4.808 4.630 4.464 4.310 4.167 4.032 3.906 2.500 2.404 2.315 2.232 2.155 2.083 2.016 1.953 1.250 1.202 1.157 1.116 1.078 1.042 1.008 0.977 38 39 3a 3b 3c 3d 3e 3f 4.386 4.310 4.237 4.167 4.098 4.032 3.968 3.907 2.193 2.155 2.119 2.083 2.049 2.016 1.984 1.953 1.096 1.078 1.059 1.042 1.025 1.008 0.992 0.977 0.548 0.539 0.530 0.521 0.512 0.504 0.496 0.488 table 18-1 buzzer frequency (khz unit)
mc80f0208/16/24 preliminary 86 mar. 2005 ver 0.2 19. interrupts the mc80f0208/16/24 interrupt circui ts consist of interrupt en- able register (ienh, ienl), interrupt request flags of irqh, irql, priority circuit, and master enable flag (?i? flag of psw). fifteen interrupt sources are provided. the configuration of inter- rupt circuit is shown in figure 19-1 and interrupt priority is shown in table 19-1. the external interrupts int0 ~ in t3 each can be transition-acti- vated (1-to-0 or 0-to-1 transiti on) by selection ieds register. the flags that actually generate these interrupts are bit int0if, int1if, int2if and int3if in register irqh. when an external interrupt is generated, the genera ted flag is cleared by the hard- ware when the service routine is vectored to only if the interrupt was transition-activated. the timer 0 ~ timer 4 interrupt s are generated by t0if, t1if, t2if, t3if and t4if which is set by a match in their respective timer/counter register. the basic interval timer interr upt is generated by bitif which is set by an overflow in the timer register. the ad converter interrupt is ge nerated by adcif which is set by finishing the analog to digital conversion. the watchdog timer and watch time r interrupt is generated by wdtif and wtif which is set by a match in watchdog timer register or watch timer register. the ifr(interrupt flag register) is used for discrimination of th e interrupt source among these two watchdog timer and wa tch timer interrupt. figure 19-1 block diagram of interrupt uart0 tx/rx int2 int1 int0 int0if ienh interrupt enable interrupt enable irqh irql internal bus line register (lower byte) internal bus line register (higher byte) release stop/sleep to cpu interrupt master enable flag i-flag ienl priority control i-flag is in psw, it is cleared by ?di?, set by ?ei? instruction. when it goes interrupt service, i-flag is cleared by hardware, thus any other interrupt are inhibited. when interrupt service is completed by ?reti? instruction, i-flag is set to ?1? by hardware. [0ea h ] [0ec h ] [0ed h ] int1if int2if int3if uart0if t0if sioif int3 uart1 tx/rx timer 0 serial uart1if timer 1 t1if t4if t3if timer 2 timer 3 timer 3 t2if a/d converter adcif bitif wtif watchdog timer bit watch timer wdtif [0eb h ] communication interrupt vector address generator
preliminary mc80f0208/16/24 mar. 2005 ver 0.2 87 the basic interval timer interrupt is generated by bitif which is set by a overflow in th e timer counter register. the uart0 receive/transmit inte rrupt is generated by uart0if is set by completion of uart0 data reception or transmission. the ifr(interrupt flag register) is used for discrimination of the interrupt source among these two uart0 receive and uart0 transmit interrupt. the sio interrupt is generated by sioif which is set by comple- tion of sio data rece ption or transmission. the interrupts are controlled by the interrupt master enable flag i-flag (bit 2 of psw on figure 8-3), the interrupt enable register (ienh, ienl), and the interrupt request flags (in irqh and irql) except power-on reset and software brk interrupt. the table 19-1 shows the interrupt priority. vector addresses are shown in figu re 8-6. interrupt enable regis- ters are shown in figure 19-2. thes e registers are composed of in- terrupt enable flags of each interrupt source and these flags determines whether an interrupt will be accepted or not. when enable flag is ?0?, a corresponding interrupt source is prohibited. note that psw contains also a master enable bit, i-flag, which disables all in terrupts at once. figure 19-2 interrupt enable flag register reset/interrupt symbol priority hardware reset external interrupt 0 external interrupt 1 external interrupt 2 external interrupt 3 uart0 rx/tx interrupt uart1 rx/tx interrupt serial input/output timer/counter 0 timer/counter 1 timer/counter 2 timer/counter 3 timer/counter 4 adc interrupt watchdog/watch timer basic interval timer reset int0 int1 int2 int3 uart0 uart1 sio timer 0 timer 1 timer 2 timer 3 timer 4 adc wdt_wt bit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 table 19-1 interrupt priority int3e r/w int0e timer/counter 0 interrupt enable flag initial value: 0000 0000 b address: 0ea h ienh int1e msb lsb sioe t0e uart0e int2e r/w r/w serial communication interrupt enable flag uart1 tx/rx interrupt enable flag external interrupt 0 enable flag uart0 tx/rx interrupt enable flag r/w r/w r/w r/w r/w external interrupt 1 enable flag external interrupt 2 enable flag external interrupt 3 enable flag r/w t1e initial value: 0000 0000 b address: 0eb h ienl t2e msb r/w timer/counter 4 interrupt enable flag timer/counter 3 interrupt enable flag r/w r/w timer/counter 2 interrupt enable flag timer/counter 1 interrupt enable flag lsb r/w adce wdte r/w r/w r/w t3e t4e wte bite basic interval timer interrupt enable flag watch timer interrupt enable flag watchdog timer interrupt enable flag a/d converter interrupt enable flag uart1e
mc80f0208/16/24 preliminary 88 mar. 2005 ver 0.2 figure 19-3 interrupt request flag register & interrupt flag register 19.1 interrupt sequence an interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to ?0? by a reset or an instruction. inter- rupt acceptance sequence requires 8 cycles of f xin (2 s at f x- in =4mhz) after the completion of the current instruction execution. the interrupt service task is terminated upon execu- tion of an interrupt re turn instruction [reti]. int3if r/w int0if timer/counter 0 interrupt request flag initial value: 0000 0000 b address: 0ec h irqh int1if msb lsb sioif t0if uart0if uart1if int2if r/w r/w serial communication interrupt request flag uart1tx/rx interrupt request flag external interrupt 3 request flag uart0 tx/rx interrupt request flag r/w r/w r/w r/w r/w external interrupt 2 request flag external interrupt 1 request flag external interrupt 0 request flag r/w t1if initial value: 0000 0000 b address: 0ed h irql t2if msb r/w timer/counter 4 interrupt request flag timer/counter 3 interrupt request flag r/w r/w timer/counter 2 interrupt request flag timer/counter 1 interrupt request flag lsb r/w adcif wdtif r/w r/w r/w t3if t4if wtif bitif basic interval timer interrupt request flag watch timer interrupt request flag watchdog timer interrupt request flag a/d converter interrupt request flag note1 : in case of using interrupts of watchdog timer and watch timer together, it is necessary to check ifr in interrupt service routine to find out which interrupt is occurred, because the watchdog timer and watch timer is shared with interrupt vector address. these flag bits must be cleared by software after read- ing this register . r/w - initial value: --00 0000 b address: 0df h ifr - msb r/w uart0 tx interrupt occurred flag note3 uart0 rx interrupt occurred flag note3 lsb r/w r/w r/w r/w rx0iof tx0iof wtiof wdt interrupt occurred flag note1 wt interrupt occurred flag note1 uart1 tx interrupt occurred flag note2 uart1 rx interrupt occurred flag note2 rx1iof tx1iof wdtiof note2 : in case of using interrupts of uart1 tx and uart1 rx together, it is necessary to check ifr in interrupt service routine to find out which interrupt is occu rred, because the uart1 tx and uart1 rx is shared with interrupt vector address. these flag bits must be cleared by software after reading this register . note3 : in case of using interrupts of uart0 tx and uart0 rx together, it is necessary to check ifr in interrupt service routine to find out which interrupt is occu rred, because the uart0 tx and uart0 rx is shared with interrupt vector address. these flag bits must be cleared by software after reading this register .
preliminary mc80f0208/16/24 mar. 2005 ver 0.2 89 19.1.1 interrupt acceptance 1. the interrupt master enable flag (i-flag) is cleared to ?0? to temporarily disable the acceptance of any follow- ing maskable interrupts. when a non-maskable inter- rupt is accepted, the ac ceptance of any following interrupts is temporarily disabled. 2. interrupt request flag for the interrupt source accepted is cleared to ?0?. 3. the contents of the prog ram counter (return address) and the program status word are saved (pushed) onto the stack area. the stack po inter decreases 3 times. 4. the entry address of the interrupt service program is read from the vector table address and the entry address is loaded to the program counter. 5. the instruction stored at th e entry address of the inter- rupt service program is executed. figure 19-4 timing chart of interrupt acceptance and interrupt return instruction a interrupt request is not accepted until the i-flag is set to ?1? even if a requested interrupt has higher priority than that of the current interrupt being serviced. when nested interrupt service is required, th e i-flag should be set to ?1? by ?ei? instruction in the interrupt service program. in this case, acceptable interrupt source s are selectively enabled by the individual interrupt enable flags. 19.1.2 saving/restoring general-purpose register during interrupt acceptance proc essing, the program counter and the program status word are auto matically saved on the stack, but accumulator and other registers ar e not saved itself. these regis- ters are saved by the software if necessary. also, when multiple interrupt services are nested, it is necessary to avoid using the same data memory area for saving registers. the following method is used to save/restore the general-purpose registers. example: register save us ing push and pop instructions v.l. system clock address bus pc sp sp-1 sp-2 v.h. new pc v.l. data bus not used pch pcl psw adl op code adh instruction fetch internal read internal write interrupt processing step interrupt service task v.l. and v.h. are vector addresses. adl and adh are start addresses of interrupt service routine as vector contents. basic interval timer 012 h 0e3 h 0ffe0 h 0ffe1 h 0e h 2e h 0e312 h 0e313 h entry address correspondence between vector table address for bit interrupt and the entry address of the interrupt service program. vector table address intxx: push a push x push y ;save acc. ;save x reg. ;save y reg.
mc80f0208/16/24 preliminary 90 mar. 2005 ver 0.2 general-purpose register save/res tore using push and pop instruc- tions; 19.2 brk interrupt software interrupt can be invoked by brk instruction, which has the lowest priority order. interrupt vector address of brk is shared with the vector of tcall 0 (refer to program memory section). when brk inter- rupt is generated, b-flag of psw is set to distinguish brk from tcall 0. each processing step is determin ed by b-flag as shown in figure 19-5. figure 19-5 execution of brk/tcall0 19.3 shared interrupt vector in case of using interrupts of watchdog timer and watch timer together, it is necessary to chec k ifr in interrupt service routine to find out which interrupt is occurred, because the watchdog timer and watch timer is shared wi th interrupt vector address. these flag bits must be cleared by software after reading this reg- ister. in case of using interrupts of uart0 tx and uart0 rx togeth- er, it is necessary to check ifr in interrupt service routine to find out which interrupt is occurred, because the uart0 tx and uart0 rx is shared with interr upt vector addr ess. these flag bits must be cleared by software after reading this register. in case of using interrupts of uart1 tx and uart1 rx togeth- er, it is necessary to check ifr in interrupt service routine to find out which interrupt is occurred, because the uart1 tx and uart1 rx is shared with interr upt vector addr ess. these flag bits must be cleared by software after readi ng this register. each interrupt processing pop y pop x pop a reti ;restore y reg. ;restore x reg. ;restore acc. ;return main task interrupt service task saving registers restoring registers acceptance of interrupt interrupt return b-flag brk interrupt routine reti tcall0 routine ret brk or tcall0 =0 =1
preliminary mc80f0208/16/24 mar. 2005 ver 0.2 91 processing step is determined by ifr as shown in figure 19-6. figure 19-6 software flowchart of shared interrupt vector 19.4 multi interrupt if two requests of different priority levels are received simulta- neously, the request of higher prio rity level is serviced. if re- quests of the interrupt are received at the same time simultaneously, an internal pol ling sequence determines by hard- ware which request is serviced . however, multiple processing through software for special featur es is possible. generally when an interrupt is accepted, the i-flag is cleared to di sable any further interrupt. but as user sets i-flag in interrupt routine, some further interrupt can be serviced even if certain interrupt is in progress. figure 19-7 execution of multi interrupt wdtif wdt interrupt wdt or wt interrupt request =0 =1 routine clear wdtif wtif wdt interrupt reti =0 =1 routine clear wtif tx0iof(tx1iof) tx0(tx1) interrupt uart0(uart1) interrupt request =0 =1 routine clear tx0iof(tx1iof) rx0iof(rx1iof) rx0(rx1) interrupt reti =0 =1 routine clear rx0iof(rx1iof) enable int0 timer 1 service int0 service main program service occur timer1 interrupt occur int0 ei disable other enable int0 enable other in this example, the int0 interrupt can be serviced without any pending, even timer1 is in progress. because of re-setting the interrupt enable registers ienh,ienl and master enable ?ei? in the timer1 routine.
mc80f0208/16/24 preliminary 92 mar. 2005 ver 0.2 example: during timer1 interrupt is in progress, int0 interrupt serviced without any suspend. timer1: push a push x push y ldm ienh,#80h ; enable int0 only ldm ienl,#0 ; disable other int. ei ; enable interrupt : : : : : : ldm ienh,#0ffh ; enable all interrupts ldm ienl,#0ffh pop y pop x pop a reti 19.5 external interrupt the external interrupt on int0, int1, int2 and int3 pins are edge triggered depending on the e dge selection regi ster ieds (ad- dress 0ee h ) as shown in figure 19-8. the edge detection of external in terrupt has three transition acti- vated mode: rising edge, fa lling edge, and both edge. figure 19-8 external interrupt block diagram int0 ~ int3 are multiplexed with general i/o ports (r10, r11, r12, r50). to use as an external interrupt pin, the bit of port se- lection register psr0 should be set to ?1? correspondingly. example: to use as an int0 and int2 : ; **** set external interrupt port as pull-up state. ldm pu1,#0000_0101b ; ; **** set port as an external interrupt port ldm psr0,#0000_0101b ; ; **** set falling-edge detection ldm ieds,#0001_0001b : response time the int0 ~ int3 edge are latched into int0if ~ int3if at every machine cycle. the values are not actually polled by the circuitry until the next machine cycle. if a request is active and conditions are right for it to be acknowledge d, a hardware subroutine call to the requested service routine will be the next instruction to be ex- ecuted. the div itself takes twel ve cycles. thus, a minimum of twelve complete machine cycles elapse between activation of an external interrupt request and th e beginning of execution of the first instruction of the service routine. figure 19-9 shows interr upt response timings. int0if int0 pin int0 interrupt int1if int1 pin int1 interrupt int2if int2 pin int2 interrupt ieds [0eeh] int3if int3 pin int3 interrupt edge selection register 2 2 2 2 01 10 11 01 10 11 01 10 11 01 10 11
preliminary mc80f0208/16/24 mar. 2005 ver 0.2 93 figure 19-9 interrupt response timing diagram figure 19-10 ieds register an d port selectio n register psr0 interrupt goes active interrupt latched interrupt processing interrupt routine 8 f xin max. 12 f xin btcl wwwwwwww ec1e - pwm3o int1e 0: r10 1: int0 initial value: 0-00 0000 b address: 0f8 h psr0 ec0e int0e int2e int3e 0: r11 1: int1 0: r12 1: int2 0: r50 1: int3 0: r54 1: pwm3o/t3o 0: r51 1: ec1 0: r15 1: ec0 lsb msb btcl wwwwwwww ied2h ied3l ied3h ied0h initial value: 00 h address: 0ee h ieds ied2l ied0l ied1l ied1h lsb msb edge selection register 00: reserved 01: falling (1-to-0 transition) 10: rising (0-to-1 transition) 11: both (rising & falling) int0 int1 int2 int3
mc80f0208/16/24 preliminary 94 mar. 2005 ver 0.2 20. operation mode the system clock controller st arts or stops the main-frequency clock oscillator. the op erating mode is generally divided into the main active mode. figure 20-1 shows the operating mode transi- tion diagram. system clock control is performe d by the system clock mode reg- ister, scmr. during reset, this register is initialized to ?0? so that the main-clock operating mode is selected. main active mode this mode is fast-frequency operating mode. the cpu and the peripheral hardware are operate d on the high-frequency clock. at reset release, this mode is invoked. sleep mode in this mode, the cpu clock stops while peripherals and the os- cillation source continues to operate normally. stop mode in this mode, the system opera tions are all stopped, holding the internal states valid immediately before the stop at the low power consumption level. the main osci llation source stops, but the sub clock oscillation and watch timer by sub cl ock and rc-oscillated watchdog timer don?t stop. figure 20-1 operating mode 20.1 operation mode switching in the main active mode, only the high-frequency clock oscillator is used. in the sub active mode , the low-frequency clock oscilla- tion is used, so the low power voltage operation or the low power consumption operation can be enabled. instruction execution does not stop during the change of operation mode. in this case, some peripheral hardware capabilities may be affected. for de- tails, refer to the descript ion of the relevant operation. the following describes the swit ching between the main active mode and the sub active mode. du ring reset, th e system clock mode register is initialized at the main active mode. it must be set to the sub active mode for reducing the power consumption. shifting from the normal operation to the sleep mode if the cpu clock stops and the sl eep mode is invoked, the cpu stops while other periphera ls are operate normally. the ways of release from this mode are by setting the reset pin to low and all available interrupts. for more detail, see "21. power saving operation" on page 95. shifting from the normal operation to the stop mode if the main-frequency cl ock oscillation stops and the stop mode is invoked, the cpu stops and othe r peripherals are stop too. but sub-frequency clock oscillation ope rate continuously if enabled previously. after the stop operation is released by reset, the op- eration mode is changed to main active mode. the methods of release from this mode are reset, watch timer, timer/event counter, sio(external clock), uart, and external interrupt. for more details, see "21. power saving operation" on page 95. note: in the stop and sleep operating modes, the pow- er consumption by the oscillator and the internal hardware is reduced. however, the power for the pin interface (de- pending on external circuitry and program) is not directly associated with the low-power consumption operation. this must be considered in system design as well as interface circuit design. main active mode main : oscillation or stop sub : oscillation main : oscillation sub : oscillation or stop stop / sleep mode * note1 / * note2 system clock : main system clock : stop * note1 : stop released by reset, watch timer, watchdog timer sio (external clock), uart0, uart1 * note2 : sleep released by reset, or all interrupts * note3 * note3 : 1) stop mode admission 2) sleep mode admission ldm sscr, #5ah stop ldm sscr, #0fh nop nop timer(event counter), external interrupt,
preliminary mc80f0208/16/24 mar. 2005 ver 0.2 95 21. power saving operation the mc80f0208/16/24 has two powe r-down modes. in power- down mode, power consumption is reduced considerably. for ap- plications where power consumpt ion is a critical factor, device provides two kinds of power savi ng functions, stop mode and sleep mode. table 21-1 shows the status of each power saving mode. sleep mode is entered by the sscr register to ?0fh?., and stop mode is entered by stop instruction after the sscr register to ?5ah?. 21.1 sleep mode in this mode, the internal osci llation circuits remain active. oscillation continues and peripherals are operate normally but cpu stops. movement of all pe ripherals is shown in table 21-1. sleep mode is entere d by setting the sscr regi ster to ?0fh?. it is released by reset or interrupt. to be released by interrupt, in- terrupt should be enable d before sleep mode. figure 21-1 stop and sleep control register release the sleep mode the exit from sleep mode is ha rdware reset or all interrupts. reset re-defines all the control registers but does not change the on-chip ram. interrupts allow both on-chip ram and control registers to retain their values. if i-flag = 1, the normal interrupt response takes place. if i-flag = 0, the chip will resume execution starting with the instruction fol- lowing the sleep instruction. it wi ll not vector to interrupt serv- ice routine. (refer to figure 21-4) when exit from sleep mode by reset, enough oscillation stabi- lization time is requi red to normal operation. figure 21-3 shows the timing diagram. when releas ed from the sleep mode, the basic interval timer is activated on wake-up. it is increased from 00 h until ff h . the count overflow is set to start normal opera- tion. therefore, before sleep in struction, user must be set its relevant prescaler divide ratio to have long enough time (more than 20msec). this guarantees that oscillator has started and sta- bilized. by interrupts, exit from sleep mode is shown in figure 21-2. by reset, exit from sleep m ode is shown in figure 21-3. 76543210 initial value: 0000 0000 b address: 0f5 h sscr w power down control 5a h : stop mode 0f h : sleep mode w w w w w w w note : to get into stop mode, sscr must be set to 5ah just before stop instruction execution. at stop mode, stop & sleep control register (sscr) value is cleared automatically when released. to get into sleep mode, sscr must be set to 0fh .
mc80f0208/16/24 preliminary 96 mar. 2005 ver 0.2 . figure 21-2 sleep mode release timing by external interrupt figure 21-3 timing of sl eep mode release by reset 21.2 stop mode in the stop mode, the main oscill ator, system clock and peripher- al clock is stopped, but the sub clock oscillation and watch timer by sub clock and rc-oscillated wa tchdog timer continue to oper- ate. with the clock frozen, all functions are stopped, but the on- chip ram and control registers are held. the port pins out the values held by their respective po rt data register, port direction registers. oscillator stops and th e systems internal operations are all held up. ? the states of the ram, registers, and latches valid immediately before the system is put in the stop state are all held. ? the program counter stop the address of the instruction to be execut ed after the instruction "stop" which starts the stop operating mode. note: the stop mode is activated by execution of stop instruction after setting the sscr to ?5a h ?. (this register should be written by byte operatio n. if this register is set by bit manipulation instruction, for example "set1" or "clr1" in- struction, it may be undesired operation) in the stop mode of operation, v dd can be reduced to minimize power consumption. care must be taken, however, to ensure that v dd is not reduced before the stop mode is invoked, and that v dd is restored to its normal ope rating level, before the stop mode is terminated. oscillator (x in pin) ~ ~ normal operation sleep operation ~ ~ ~ ~ ~ ~ ~ ~ external interrupt internal clock sleep instruction executed ~ ~ normal operation ~ ~ ~ ~ ~ ~ sleep instruction stabilization time t st = 65.5ms @4mhz internal ~ ~ ~ ~ ~ ~ reset reset oscillator (x in pin) ~ ~ cpu clock ~ ~ ~ ~ execution normal operation sleep operation normal operation
preliminary mc80f0208/16/24 mar. 2005 ver 0.2 97 the reset should not be activated before v dd is restored to its normal operating level, and must be held active long enough to allow the oscillator to restart and stabilize. note: after stop instruction, at least two or more nop in- struction should be written. ex) ldm ckctlr,#0fh ;more than 20ms ldm sscr,#5ah stop nop ;for stabilization time nop ;for stabilization time in the stop operation, the dissi pation of the power associated with the oscillator and the intern al hardware is lowered; however, the power dissipation associated with the pin interface (depend- ing on the external circuitry and program) is not directly deter- mined by the hardware operation of the stop feature. this point should be little current flows when the input level is stable at the power voltage level (v dd /v ss ); however, when the input level gets higher than the power voltage level (by approximately 0.3 to 0.5v), a current begins to flow. therefore, if cutting off the out- put transistor at an i/o port puts the pin signal into the high-im- pedance state, a current flow ac ross the ports input transistor, requiring to fix the level by pull-up or other means. release the stop mode the source for exit from stop m ode is hardware reset, external interrupt, timer(ec0,1), watch timer, wdt, sio or uart. re- set re-defines all the control registers but does not change the on- chip ram. external interrupts allow both on-chip ram and control registers to retain their values. if i-flag = 1, the normal interrupt response takes place. if i-flag = 0, the chip will resume execution starting with the instruction fol- lowing the stop instruction. it will not vector to interrupt service routine. (refer to figure 21-4) when exit from stop mode by ex ternal interrupt , enough oscilla- tion stabilization time is require d to normal operation. figure 21- 5 shows the timing diagram. when released from the stop mode, the basic interval timer is activat ed on wake-up. it is increased from 00 h until ff h . the count overflow is set to start normal op- peripheral stop mode sleep mode cpu stop stop ram retain retain basic interval timer halted operates continuously watchdog timer stop (only operates in rc-wdt mode) stop watch timer stop stop timer/counter halted(only when the event counter mode is enabled, timer operates normally) operates continuously buzzer, adc stop stop sio only operate with external cloc k only operate with external clock uart only operate with external cloc k only operate with external clock oscillator stop(x in =l, x out =h) oscillation sub oscillator oscillation oscillation i/o ports retain retain control registers retain retain internal circuit stop mode sleep mode prescaler retain active address data bus retain retain release source reset, timer(ec0,1), sio, uart0(using aclk0), uart1(using aclk1) watch timer( rc-wdt mode), watchdog timer( rc-wdt mode), external interrupt reset, all interrupts table 21-1 peripheral operation during power saving mode
mc80f0208/16/24 preliminary 98 mar. 2005 ver 0.2 eration. therefore, before stop in struction, user must be set its relevant prescaler divide ratio to have long enough time (more than 20msec). this guarantees that oscillator has started and sta- bilized. by reset, exit from stop mode is shown in figure 21-6. figure 21-4 stop releasing flow by interrupts . figure 21-5 stop mode release timing by external interrupt ienh or ienl ? =0 =1 stop instruction stop mode interrupt request stop mode release i-flag =1 interrupt service routine next instruction =0 master interrupt enable bit psw[2] corresponding interrupt enable bit (ienh, ienl) before executing stop instruction, basic interval timer must be set oscillator (x in pin) ~ ~ n 0 bit counter n+1 n+2 n+3 ~ ~ normal operation stop operation normal operation 1 fe ff 0 12 ~ ~ ~ ~ ~ ~ t st > 20ms ~ ~ ~ ~ external interrupt internal clock clear stop instruction executed ~ ~ ~ ~ ~ ~ properly by software to get stabilization time which is longer than 20ms. by software ~ ~ stabilization time
preliminary mc80f0208/16/24 mar. 2005 ver 0.2 99 figure 21-6 timing of stop mode release by reset 21.3 stop mode at internal rc-oscillated watchdog timer mode in the internal rc-oscillated watchdog timer mode, the on-chip oscillator is stopped. but internal rc oscillation circuit is oscil- lated in this mode. the on-chip ram and control registers are held. the port pins out the values held by their respective port data register, port direction registers. the internal rc-oscillated wat chdog timer mode is activated by execution of stop instructi on after setting the bit rcwdt of ckctlr to "1". (this register should be writt en by byte opera- tion. if this register is set by bit manipulation instruction, for ex- ample "set1" or "clr1" instructi on, it may be undesired operation) note: caution: after stop instruction, at least two or more nop instruction should be written ex) ldm wdtr,#1111_1111b ldm ckctlr,#0010_1110b ldm sscr,#0101_1010b stop nop ;for stabilization time nop ;for stabilization time the exit from internal rc-oscillated watchdog timer mode is hardware reset or external inte rrupt or watchdog timer interrupt (at rc-watchdog timer mode). rese t re-defines all the control registers but does not change the on-chip ram. external inter- rupts allow both on-chip ram a nd control registers to retain their values. if i-flag = 1, the normal interrupt response takes place. in this case, if the bit wdton of ckc tlr is set to "0" and the bit wdte of ienh is set to "1", the device will execute the watch- dog timer interrupt service routine(figure 8-6). however, if the bit wdton of ckctlr is set to "1", the device will generate the internal reset signal and ex ecute the reset processing(figure 21-8). if i-flag = 0, the chip will resume execution starting with the instruction following the stop instruction. it will not vector to interrupt service routin e.(refer to figure 21-4) when exit from stop mode at internal rc-oscillated watchdog timer mode by external interrupt , the oscillation stabilization time is required to normal operation. figure 21-7 shows the tim- ing diagram. when release the internal rc-oscillated watchdog timer mode, the basic interval ti mer is activated on wake-up. it is increased from 00 h until ff h . the count overflow is set to start normal operation. therefore, before stop instruction, user must be set its relevant pr escaler divide ratio to have long enough time (more than 20msec). this guarantees that oscillator has started and stabilized. by reset, exit from internal rc-oscillated watch- dog timer mode is shown in figure 21-8. ~ ~ stop mode time can not be control by software oscillator (xi pin) ~ ~ ~ ~ ~ ~ stop instruction execution stabilization time t st = 65.5ms @4mhz internal clock internal ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ reset reset
mc80f0208/16/24 preliminary 100 mar. 2005 ver 0.2 figure 21-7 stop mode release at internal rc-wd t mode by external inte rrupt or wdt interrupt figure 21-8 internal rc-wdt mode releasing by reset ~ ~ stop mode normal operation oscillator (x in pin) ~ ~ ~ ~ n+1 nn+2 00 01 fe ff 00 00 n-1 n-2 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ clear basic interval timer stop instruction execution normal operation stabilization time t st > 20ms internal clock external interrupt bit counter ~ ~ internal rc clock ( or wdt interrupt ) at rc-wdt mode ~ ~ oscillator (x in pin) ~ ~ ~ ~ ~ ~ ~ ~ internal clock internal rc clock time can not be control by software ~ ~ stop instruction execution stabilization time t st = 65.5ms @4mhz internal ~ ~ ~ ~ ~ ~ reset by wdt reset reset rcwdt mode
preliminary mc80f0208/16/24 mar. 2005 ver 0.2 101 21.4 minimizing current consumption the stop mode is designed to reduce power consumption. to minimize current drawn during st op mode, the user should turn- off output drivers that are sourcing or sinking current, if it is prac- tical. figure 21-9 application example of unused input port figure 21-10 application example of unused output port note: in the stop operation, the power dissipation asso- ciated with the oscillator and the internal hardware is low- ered; however, the power diss ipation associated with the pin interface (depending on the external circuitry and pro- gram) is not directly determined by the hardware operation of the stop feature. this point should be little current flows when the input level is stable at the power voltage level (v dd /v ss ); however, when the in put level becomes higher than the power voltage level (by approximately 0.3v), a cur- rent begins to flow. therefore, if cutting off the output tran- sistor at an i/o port puts the pin signal into the high- impedance state, a current flow across the ports input tran- sistor, requiring it to fix the level by pull-up or other means. it should be set properly in orde r that current flow through port doesn't exist. first consider the port setting to input mode. be sure that there is input pin v dd gnd i v dd x weak pull-up current flows v dd internal pull-up input pin i v dd x very weak current flows v dd o o open open i=0 o i=0 o gnd when port is configured as an input, input level should be closed to 0v or 5v to avoid power consumption. output pin gnd i in the left case, much current flows from port to gnd. x on off output pin gnd i in the left case, tr. base current flows from port to gnd. i=0 x off on v dd l on off open gnd v dd l on off to avoid power consumption, there should be low output on off o o v dd o to the port .
mc80f0208/16/24 preliminary 102 mar. 2005 ver 0.2 no current flow after considering its relationship with external circuit. in input mode, the pi n impedance viewing from external mcu is very high that the current doesn?t flow. but input voltage level should be v ss or v dd . be careful that if unspecified voltage, i. e. if uncertain vol tage level (not v ss or v dd ) is applied to input pin, ther e can be little current (max. 1ma at around 2v) flow. if it is not appropriate to set as an input mode, then set to output mode considering there is no current flow. the port setting to high or low is decided by consid ering its relations hip with exter- nal circuit. for example, if there is external pull-up resistor then it is set to output mode, i.e. to high, and if there is external pull- down register, it is set to low.
preliminary mc80f0208/16/24 mar. 2005 ver 0.2 103 22. oscillator circuit the mc80f0208/16/24 have oscillation circuits internally. x in and x out are input and output for fre quency. respectively, in- verting amplifier which can be configured for being used as an on-chip oscillator, as shown in figure 22-1. figure 22-1 oscillation circuit oscillation circuit is designed to be used either with a ceramic resonator or crystal os cillator. since each cr ystal and ceramic res- onator have their own characteris tics, the user should consult the crystal manufacturer for appropri ate values of external compo- nents. in addition, see figure 22-2 for the layout of the crystal. note: minimize the wiring length. do not allow the wiring to intersect with other signal conductors. do not allow the wir- ing to come near changing high current. set the potential of the grounding position of the oscillator capacitor to that of v ss . do not ground it to any ground pattern where high cur- rent is present. do not fetc h signals from the oscillator. figure 22-2 layout of oscillator pcb circuit x out x in v ss c1 c2 x out x in external clock open external oscillator crystal or ceramic oscillator 8mhz recommended c1,c2 = 20pf 10pf crystal oscillator ceramic resonator c1,c2 = 20pf 10pf x out x in
mc80f0208/16/24 preliminary 104 mar. 2005 ver 0.2 23. reset the mc80f0208/16/24 have four t ypes of reset generation pro- cedures; they are an external re set input, a watch-dog timer reset, power fail processor reset, and address fail re set. table 23-1 shows on-chip hardware in itialization by reset action. table 23-1 initializing internal status by reset action external reset input the reset input is the reset pin, which is the input to a schmitt trigger. a reset in accomp lished by holding the reset pin low for at least 8 oscillat or periods, within th e operating voltage range and oscillation stable, it is applied, and the internal state is initial- ized. after reset, 65.5ms (at 4 mh z) add with 7 oscillator periods are required to start execution as shown in figure 23-2. internal ram is not affe cted by reset. when v dd is turned on, the ram content is indeterminat e. therefore, this ram should be initialized before read or tested it. when the reset pin input goes to high, the reset operation is re- leased and the program execution starts at the vector address stored at addresses fffe h - ffff h . a connection for simple power-on -reset is shown in figure 23-1. figure 23-1 simple power-on-reset circuit figure 23-2 timing diagram after reset address fail reset the address fail reset is the function to reset the system by checking code access of abnorm al and unwished address caused by erroneous program code itself or external noise, which could not be returned to normal oper ation and would become malfunc- tion state. if the cpu tries to fetch the instruction from ineffective code area or ram area, the address fail reset is occurred. please refer to figure 11-2 for se tting address fail option. on-chip hardware initial value on-chip hardware initial value program counter (pc) (ffff h ) - (fffe h ) peripheral clock off ram page register (rpr) 0 watchdog timer disable g-flag (g) 0 control registers refer to table 8-1 on page 27 operation mode main-frequency cl ock power fail detector disable 7036p v cc 10uf + 10k ? to the reset pin main program oscillator (x in pin) ? ? fffe ffff stabilization time t st =65.5ms at 4mhz reset address data 1 2 3 4 5 6 7 ?? start ? ? ? fe ? adl adh op bus bus reset process step ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ t st = x 256 f xin 1024 1
preliminary mc80f0208/16/24 mar. 2005 ver 0.2 105 24. power fail processor the mc80f0208/16/24 has an on-ch ip power fail detection cir- cuitry to immunize against power noise. a configuration register, pfdr, can enable or disable th e power fail detect circuitry. whenever v dd falls close to or below power fail voltage for 100ns, the power fail situation ma y reset or freeze mcu accord- ing to pfdm bit of pfdr. refer to ?figure 24-1 power fail volt- age detector register? on page 105. in the in-circuit emulator, power fail function is not implemented and user can not experi ment with it. therefore, after final devel- opment of user program, this function may be experimented or evaluated. note: user can select power fail voltage level according to pfs0, pfs1 bit of config register(703fh) at the flash (mc80f0208/16/24) but must select the power fail voltage level to define pfd option of "mask order & verification sheet" at the mask chip(mc80c0208/16/24), because the power fail voltage level of mask chip (mc80c0208/16/24) is determined according to mask option. note: if power fail voltage is selected to 2.4v or 2.7v on below 3v operation, mcu is freezed at all the times. table 24-1 power fail processor figure 24-1 power fail voltage detector register power fail function flash mask enable/disable pfden flag pfden flag level selection pfs0 bit pfs1 bit mask option pfdm 76543210 pfds initial value: ---- -000 b address: 0f7 h pfdr r/w r/w r/w pfden pfd operation mode 0 : mcu will be frozen by power fail detection 1 : mcu will be reset by power fail detection pfd enable bit 0: power fail detection disable 1: power fail detection enable power fail status 0: normal operate 1: set to ?1? if power fail is detected * cautions : be sure to set bits 3 through 7 to ?0?. -----
mc80f0208/16/24 preliminary 106 mar. 2005 ver 0.2 figure 24-2 example s/w of reset flow by power fail figure 24-3 power fail processor situations (at 4mhz operation) function execution initialize ram data pfds =1 no reset vector initialize all ports initialize registers ram clear yes skip the initial routine pfds = 0 internal reset internal reset internal reset v dd v dd v dd v pfd max v pfd min v pfd max v pfd min v pfd max v pfd min 65.5ms 65.5ms t < 65.5ms 65.5ms when pfdm = 1
preliminary mc80f0208/16/24 mar. 2005 ver 0.2 107 25. flash programming the device configuration area can be programmed or left un- programmed to select device confi guration such as security bit. this area is not accessible dur ing normal executio n but is read- able and writable during flash program / verify mode. the de- vice configuration area register is located at the address 20ff h . figure 25-1 device configuration area 25.1 lock bit the lock bit exists in device c onfiguration area register. if lock bit is programmed and user tries to read flash memory cell, the output data from the data port is 5ah that means the normal pro- tection operation of user program data.once the lock bit is pro- grammed, the user can't modify a nd read the data of user program area. 25.2 power fail detector the power fail detection provides 3 level of detection, 2.4v, 2.7v and 3.0v. the default le vel of detection is 2. 7v and this level is applied if user does not select the specific level in flash pro- gramming s/w tools. for more in formation, refer to ?24. pow- er fail processor? on page 105. 76543210 initial value: 00 h address: 20ff h config code protect (available flash version) 0 : lock disable 1 : lock enable (main cell read protection) pfd level selection 00: pfd = 2.7v 01: pfd = 2.7v pfs1 10: pfd = 3.0v 11: pfd = 2.4v ----- pfs0 lock
mc80f0208/16/24 preliminary 108 mar. 2005 ver 0.2 26. emulator eva. board setting ?? ? ?????? ? ? ? ? ? ? ? 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 v cc avdd gnd r66 r64 r62 r60 gnd r56 r54 r52 r50 gnd r46 r44 r42 r40 gnd r36 r34 r32 r30 gnd u_x out gnd vdd avdd gnd r67 r65 r63 r61 gnd r57 r55 r53 r51 gnd r47 r45 r43 r41 gnd r37 r35 r33 r31 gnd u_reset gnd 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 vdd r71 r73 r75 r77 gnd r81 r83 r85 r87 gnd r01 r03 r05 r07 gnd r11 r13 r15 r17 gnd r21 r23 r25 r27 vdd r70 r72 r74 r76 gnd r80 r82 r84 r86 gnd r00 r02 r04 r06 gnd r10 r12 r14 r16 gnd r20 r22 r24 r26 j_userb j_usera
preliminary mc80f0208/16/24 mar. 2005 ver 0.2 109 dip switch and vr setting before execute the user program, keep in your mind the below configuration dip s/w descripti on on/off setting - this connector is only used for a de vice over 32 pin. for the mc80f0208/16/24. - this connector is only used for a device under 32 pin. for the mc80f0204. sw2 1 eva. select switch must be on position. on : for the mc80f0208/16/24. off : for the mc80f0204. 2 3 av dd pin select switch these switches select the av dd source. on & off : use eva. v dd off & on : use user av dd 4 this switch select the /reset source. normally off . eva. chip can be reset by external user tar- get board. on : reset is available by either user target system board or emulator reset switch. off : reset the mcu by emulator reset switch. does not work from user target board. 5 this switch select the xout signal on/off. normally off . mcu xout pin is disconnected internally in the emulator. some circumstance user may connect this circuit. on : output xout signal off : disconnect circuit sw3 1 this switch select eva. b/d power supply source. normally mds . this switch select eva. b/d power supply source. sw4 1 2 this switch select the r22 or sx out . this switch select the r21 or sx in . these switchs sele ct the normal i/o port(off) or sub-clock (on). it is reserved for the mc80f0448. on : sx out , sx in off : r22, r21 don?t care (mc80f0208/16/24). ? ? ? on on off off on use eva. v dd use user?s av dd ? use mds power mds user mds user use user?s power ?
mc80f0208/16/24 preliminary 110 mar. 2005 ver 0.2 sw5 1 2 these switches select the r33 or x in this switch select the normal i/o port(on&off) or special function select(off&on). it is reserved for the mc80f0204. on & off : r33,r34,r35 port selected. off & on : x out , x in , /reset selected. don?t care (mc80f0208/16/24). 3 4 these switches select the r34 or x out 5 6 these switches select the r35 or /reset - this is external oscillation socket(can type. osc) this is for external clock(can type. osc). dip s/w descripti on on/off setting ? ?
preliminary mc80f0208/16/24 mar. 2005 ver 0.2 111 27. in-system programming (isp) 27.1 getting started / installation the following section details the procedure for accomplishing the installation procedure. 1. connect the serial(rs-232 c) cable between a target board and the com port of your pc. 2. configure the com port of your pc as following. 3. turn your target b/d power switch on. your target b/ d must be configured to enter the isp mode. 4. run the magnachip isp software. 5. press the reset button in th e isp s/w. if the status win- dows shows a message as "connected", all the condi- tions for isp are provided. 27.2 basic isp s/w information baudrate 115,200 data bit 8 parity no stop bit 1 flow control no
mc80f0208/16/24 preliminary 112 mar. 2005 ver 0.2 function description load hex file load the data from the selected file storage into the memory buffer. save hex file save the current data in your memory buff er to a disk storage by using the intel motorolla hex format. erase erase the data in your target mcu before programming it. blank check verify whether or not a device is in an erased or unprogrammed state. program this button enables you to place new data fr om the memory buffer in to the target device. read read the data in the target mcu into the buffer for examination. the checksum will be displayed on the checksum box. verify assures that data in the device matches data in the memory buffer. if your device is secured, a verification error is detected. option write progam the configuration data of target mcu. the security locking is performed with this button. option set the configuration data of target mcu. the security lo cking is set with this button. auto erase & program & verify. auto option write if selected with check mark, the option write is performed after erasure and write. edit buffer modify the data in the selected address in your buffer memory fill buffer fill the selected area with a data. goto display the selected page. osc. ______ mhz enter your target system?s oscillator value with discarding below point. start ______ starting address end ______ end address checksum display the checksum(hexdecimal) after reading th e target device. com port select serial port. baud rate select uart baud rate. select device sele ct target device. page up key display the previous page of your memory buffer. page down key display the higher page than the current location. table 1. isp function description
preliminary mc80f0208/16/24 mar. 2005 ver 0.2 113 27.3 hardware conditions to enter the isp mode the in-system programming (isp) is performed without remov- ing the microcontroller from the target system. the in-system programming(isp) facility consists of a series of internal hard- ware resources coupled with inte rnal firmware through the serial port. the in-system programming (isp) facility has made in-cir- cuit programming in an embedd ed application possible with a minimum of additional expense in components and circuit board area. the boot loader can be executed by holding aleb high, rst/v pp as +9v, and aclk0 with the osc. 1.8432mhz. the isp function uses five pins: txd0, rxd0, aleb, aclk0 and rst/v pp . figure 27-1 isp configuration note: considerations to implement isp function in a user target board ? the aclk0 must be connected to the specifed oscillator. ? connect the +9v to rst/vpp pin directly. ? the aleb pin must be pulled high. ? the main clk must be higher than 2mhz. v dd reset x in x out v ss r47 / txd0 r46 / rxd0 r45 / aclk0 r30 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 mc80f0208k/16k/24k isp configuration tx_data rx_data 1.8432mhz v dd v dd (+5v) +9v aleb rst/v pp x-tal 2mhz~12mhz
mc80f0208/16/24 preliminary 114 mar. 2005 ver 0.2 27.4 reference isp circuit diagram the isp s/w and h/w circuit diagram are provided at www.magnachipmcu.com . to get a isp b/d, contact to sales department. the following circuit diagram is for reference use. figure 27-2 referenc e isp circuit diagram figure 27-3 magnachip supplied isp board the ragne of v dd must be from 5.5v to 4.5 and the minimum operation fr equency is 2mhz. if the user supplied v dd is out of range, the external power is needed instead of the target system v dd . for the isp operation, power cons umption required is less than 30ma. t1in t2in r1out r2out c1+ c1- c2+ c2- t1out t2out r1in r2in v+ vcc v- gnd con1 female db9 j2 v ss j3 external v dd reset /v pp mcu_txd mcu_rxd v dd v ss 10uf/16v 0.1uf max232 aclk_clk vcc out gnd osc x1 1.8432mhz 22 ? 0.1uf 22 ? v dd (+5v) v ss v dd (+5v) v ss 14 7 13 8 2 16 6 15 11 10 12 9 1 3 4 5 v ss 1 2 3 4 5 v dd (+5v) 6 1uf 1uf 1uf 1uf * v pp : v dd + 4v * v dd : +4.5 ~ +5.5v from pc to mcu gnd txd rxd + + + + + v dd v ss dtr v ss v ss + 10uf/35v 100 ? 1k ? 8.2k ? 10k ? 2n2907 v ss v ss v dd (+5v) 5 4 3 2 1 9 8 7 6 22 ? 22 ? v ss v ss 100pf 100pf
appendix
gms800 series mar. 2005 i a. instruction a.1 terminology list terminology description a accumulator x x - register y y - register psw program status word #imm 8-bit immediate data dp direct page offset address !abs absolute address [ ] indirect expression { } register indirect expression { }+ register indirect expression, after that, register auto-increment .bit bit position a.bit bit position of accumulator dp.bit bit position of direct page memory m.bit bit position of memory data (000 h ~0fff h ) rel relative addressing data upage u-page (0ff00 h ~0ffff h ) offset address n table call number (0~15) +addition x upper nibble expression in opcode y upper nibble expression in opcode ? subtraction multiplication / division ( ) contents expression and or exclusive or ~not assignment / transfer / shift left shift right ? exchange = equal not equal 0 bit position 1 bit position
gms800 series ii mar. 2005 a.2 instruction map low high 00000 00 00001 01 00010 02 00011 03 00100 04 00101 05 00110 06 00111 07 01000 08 01001 09 01010 0a 01011 0b 01100 0c 01101 0d 01110 0e 01111 0f 000 - set1 dp.bit bbs a.bit,rel bbs dp.bit,rel adc #imm adc dp adc dp+x adc !abs asl a asl dp tcall 0 seta1 .bit bit dp pop a push a brk 001 clrc sbc #imm sbc dp sbc dp+x sbc !abs rol a rol dp tcall 2 clra1 .bit com dp pop x push x bra rel 010 clrg cmp #imm cmp dp cmp dp+x cmp !abs lsr a lsr dp tcall 4 not1 m.bit tst dp pop y push y pcall upage 011 di or #imm or dp or dp+x or !abs ror a ror dp tcall 6 or1 or1b cmpx dp pop psw push psw ret 100 clrv and #imm and dp and dp+x and !abs inc a inc dp tcall 8 and1 and1b cmpy dp cbne dp+x txsp inc x 101 setc eor #imm eor dp eor dp+x eor !abs dec a dec dp tcall 10 eor1 eor1b dbne dp xma dp+x tspx dec x 110 setg lda #imm lda dp lda dp+x lda !abs txa ldy dp tcall 12 ldc ldcb ldx dp ldx dp+y xcn das 111 ei ldm dp,#imm sta dp sta dp+x sta !abs tax sty dp tcall 14 stc m.bit stx dp stx dp+y xax stop low high 10000 10 10001 11 10010 12 10011 13 10100 14 10101 15 10110 16 10111 17 11000 18 11001 19 11010 1a 11011 1b 11100 1c 11101 1d 11110 1e 11111 1f 000 bpl rel clr1 dp.bit bbc a.bit,rel bbc dp.bit,rel adc {x} adc !abs+y adc [dp+x] adc [dp]+y asl !abs asl dp+x tcall 1 jmp !abs bit !abs addw dp ldx #imm jmp [!abs] 001 bvc rel sbc {x} sbc !abs+y sbc [dp+x] sbc [dp]+y rol !abs rol dp+x tcall 3 call !abs test !abs subw dp ldy #imm jmp [dp] 010 bcc rel cmp {x} cmp !abs+y cmp [dp+x] cmp [dp]+y lsr !abs lsr dp+x tcall 5 mul tclr1 !abs cmpw dp cmpx #imm call [dp] 011 bne rel or {x} or !abs+y or [dp+x] or [dp]+y ror !abs ror dp+x tcall 7 dbne y cmpx !abs ldya dp cmpy #imm reti 100 bmi rel and {x} and !abs+y and [dp+x] and [dp]+y inc !abs inc dp+x tcall 9 div cmpy !abs incw dp inc y tay 101 bvs rel eor {x} eor !abs+y eor [dp+x] eor [dp]+y dec !abs dec dp+x tcall 11 xma {x} xma dp decw dp dec y tya 110 bcs rel lda {x} lda !abs+y lda [dp+x] lda [dp]+y ldy !abs ldy dp+x tcall 13 lda {x}+ ldx !abs stya dp xay daa 111 beq rel sta {x} sta !abs+y sta [dp+x] sta [dp]+y sty !abs sty dp+x tcall 15 sta {x}+ stx !abs cbne dp xyx nop
gms800 series mar. 2005 iii a.3 instruction set arithmetic / logic operation no. mnemonic op code byte no cycle no operation flag nvgbhizc 1 adc #imm 04 2 2 add with carry. 2 adc dp 05 2 3 a ( a ) + ( m ) + c 3 adc dp + x 06 2 4 4 adc !abs 07 3 4 nv--h-zc 5 adc !abs + y 15 3 5 6 adc [ dp + x ] 16 2 6 7 adc [ dp ] + y 17 2 6 8adc { x } 14 1 3 9 and #imm 84 2 2 logical and 10 and dp 85 2 3 a ( a ) ( m ) 11 and dp + x 86 2 4 12 and !abs 87 3 4 n-----z- 13 and !abs + y 95 3 5 14 and [ dp + x ] 96 2 6 15 and [ dp ] + y 97 2 6 16 and { x } 94 1 3 17 asl a 08 1 2 arithmetic shift left 18 asl dp 09 2 4 n-----zc 19 asl dp + x 19 2 5 20 asl !abs 18 3 5 21 cmp #imm 44 2 2 compare accumulator contents with memory contents ( a ) - ( m ) 22 cmp dp 45 2 3 23 cmp dp + x 46 2 4 24 cmp !abs 47 3 4 n-----zc 25 cmp !abs + y 55 3 5 26 cmp [ dp + x ] 56 2 6 27 cmp [ dp ] + y 57 2 6 28 cmp { x } 54 1 3 29 cmpx #imm 5e 2 2 compare x contents with memory contents 30 cmpx dp 6c 2 3 ( x ) - ( m ) n-----zc 31 cmpx !abs 7c 3 4 32 cmpy #imm 7e 2 2 compare y contents with memory contents 33 cmpy dp 8c 2 3 ( y ) - ( m ) n-----zc 34 cmpy !abs 9c 3 4 35 com dp 2c 2 4 1?s complement : ( dp ) ~( dp ) n-----z- 36 daa df 1 3 decimal adjust for addition n-----zc 37 das cf 1 3 decimal adjust for subtraction n-----zc 38 dec a a8 1 2 decrement n-----z- 39 dec dp a9 2 4 m ( m ) - 1 n-----z- 40 dec dp + x b9 2 5 n-----z- 41 dec !abs b8 3 5 n-----z- 42 dec x af 1 2 n-----z- 43 dec y be 1 2 n-----z- 76543210 ?0? c
gms800 series iv mar. 2005 44 div 9b 1 12 divide : ya / x q: a, r: y nv--h-z- 45 eor #imm a4 2 2 exclusive or 46 eor dp a5 2 3 a ( a ) ( m ) 47 eor dp + x a6 2 4 48 eor !abs a7 3 4 n-----z- 49 eor !abs + y b5 3 5 50 eor [ dp + x ] b6 2 6 51 eor [ dp ] + y b7 2 6 52 eor { x } b4 1 3 53 inc a 88 1 2 increment n-----zc 54 inc dp 89 2 4 m ( m ) + 1 n-----z- 55 inc dp + x 99 2 5 n-----z- 56 inc !abs 98 3 5 n-----z- 57 inc x 8f 1 2 n-----z- 58 inc y 9e 1 2 n-----z- 59 lsr a 48 1 2 logical shift right 60 lsr dp 49 2 4 n-----zc 61 lsr dp + x 59 2 5 62 lsr !abs 58 3 5 63 mul 5b 1 9 multiply : ya y a n-----z- 64 or #imm 64 2 2 logical or 65 or dp 65 2 3 a ( a ) ( m ) 66 or dp + x 66 2 4 67 or !abs 67 3 4 n-----z- 68 or !abs + y 75 3 5 69 or [ dp + x ] 76 2 6 70 or [ dp ] + y 77 2 6 71 or { x } 74 1 3 72 rol a 28 1 2 rotate left through carry 73 rol dp 29 2 4 n-----zc 74 rol dp + x 39 2 5 75 rol !abs 38 3 5 76 ror a 68 1 2 rotate right through carry 77 ror dp 69 2 4 n-----zc 78 ror dp + x 79 2 5 79 ror !abs 78 3 5 80 sbc #imm 24 2 2 subtract with carry 81 sbc dp 25 2 3 a ( a ) - ( m ) - ~( c ) 82 sbc dp + x 26 2 4 83 sbc !abs 27 3 4 nv--hzc 84 sbc !abs + y 35 3 5 85 sbc [ dp + x ] 36 2 6 86 sbc [ dp ] + y 37 2 6 87 sbc { x } 34 1 3 88 tst dp 4c 2 3 test memory contents for negative or zero, ( dp ) - 00 h n-----z- 89 xcn ce 1 5 exchange nibbles within the accumulator a 7 ~a 4 ? a 3 ~a 0 n-----z- no. mnemonic op code byte no cycle no operation flag nvgbhizc 76543210 ?0? c 76543210 c 76543210 c
gms800 series mar. 2005 v register / memory operation no. mnemonic op code byte no cycle no operation flag nvgbhizc 1 lda #imm c4 2 2 load accumulator 2 lda dp c5 2 3 a ( m ) 3 lda dp + x c6 2 4 4 lda !abs c7 3 4 5 lda !abs + y d5 3 5 n-----z- 6 lda [ dp + x ] d6 2 6 7 lda [ dp ] + y d7 2 6 8lda { x } d4 1 3 9 lda { x }+ db 1 4 x- register auto-increment : a ( m ) , x x + 1 10 ldm dp,#imm e4 3 5 load memory with immediate data : ( m ) imm -------- 11 ldx #imm 1e 2 2 load x-register 12 ldx dp cc 2 3 x ( m ) n-----z- 13 ldx dp + y cd 2 4 14 ldx !abs dc 3 4 15 ldy #imm 3e 2 2 load y-register 16 ldy dp c9 2 3 y ( m ) n-----z- 17 ldy dp + x d9 2 4 18 ldy !abs d8 3 4 19 sta dp e5 2 4 store accumulator contents in memory 20 sta dp + x e6 2 5 ( m ) a 21 sta !abs e7 3 5 22 sta !abs + y f5 3 6 -------- 23 sta [ dp + x ] f6 2 7 24 sta [ dp ] + y f7 2 7 25 sta { x } f4 1 4 26 sta { x }+ fb 1 4 x- register auto-increment : ( m ) a, x x + 1 27 stx dp ec 2 4 store x-register contents in memory 28 stx dp + y ed 2 5 ( m ) x -------- 29 stx !abs fc 3 5 30 sty dp e9 2 4 store y-register contents in memory 31 sty dp + x f9 2 5 ( m ) y -------- 32 sty !abs f8 3 5 33 tax e8 1 2 transfer accumulator contents to x-register : x a n-----z- 34 tay 9f 1 2 transfer accumulator contents to y-register : y a n-----z- 35 tspx ae 1 2 transfer stack-pointer contents to x-register : x sp n-----z- 36 txa c8 1 2 transfer x-register contents to accumulator: a x n-----z- 37 txsp 8e 1 2 transfer x-register contents to stack-pointer: sp x n-----z- 38 tya bf 1 2 transfer y-register contents to accumulator: a y n-----z- 39 xax ee 1 4 exchange x-register contents with accumulator :x ? a -------- 40 xay de 1 4 exchange y-register contents with accumulator :y ? a -------- 41 xma dp bc 2 5 exchange memory contents with accumulator 42 xma dp+x ad 2 6 ( m ) ? a n-----z- 43 xma {x} bb 1 5 44 xyx fe 1 4 exchange x-register contents with y-register : x ? y --------
gms800 series vi mar. 2005 16-bit operation bit manipulation no. mnemonic op code byte no cycle no operation flag nvgbhizc 1 addw dp 1d 2 5 16-bits add without carry ya ( ya ) + ( dp +1 ) ( dp ) nv--h-zc 2 cmpw dp 5d 2 4 compare ya contents with memory pair contents : (ya) ? (dp+1)(dp) n-----zc 3decw dp bd 2 6 decrement memory pair ( dp+1)( dp) ( dp+1) ( dp) - 1 n-----z- 4 incw dp 9d 2 6 increment memory pair ( dp+1) ( dp) ( dp+1) ( dp ) + 1 n-----z- 5 ldya dp 7d 2 5 load ya ya ( dp +1 ) ( dp ) n-----z- 6stya dp dd 2 5 store ya ( dp +1 ) ( dp ) ya -------- 7 subw dp 3d 2 5 16-bits subtract without carry ya ( ya ) - ( dp +1) ( dp) nv--h-zc no. mnemonic op code byte no cycle no operation flag nvgbhizc 1 and1 m.bit 8b 3 4 bit and c-flag : c ( c ) ( m .bit ) -------c 2 and1b m.bit 8b 3 4 bit and c-flag and not : c ( c ) ~( m .bit ) -------c 3 bit dp 0c 2 4 bit test a with memory : mm----z- 4 bit !abs 1c 3 5 z ( a ) ( m ) , n ( m 7 ) , v ( m 6 ) 5 clr1 dp.bit y1 2 4 clear bit : ( m.bit ) ?0? -------- 6 clra1 a.bit 2b 2 2 clear a bit : ( a.bit ) ?0? -------- 7 clrc 20 1 2 clear c-flag : c ?0? -------0 8 clrg 40 1 2 clear g-flag : g ?0? --0----- 9 clrv 80 1 2 clear v-flag : v ?0? -0--0--- 10 eor1 m.bit ab 3 5 bit exclusive-or c-flag : c ( c ) ( m .bit ) -------c 11 eor1b m.bit ab 3 5 bit excl usive-or c-flag and not : c ( c ) ~(m .bit) -------c 12 ldc m.bit cb 3 4 load c-flag : c ( m .bit ) -------c 13 ldcb m.bit cb 3 4 load c-flag with not : c ~( m .bit ) -------c 14 not1 m.bit 4b 3 5 bit complement : ( m .bit ) ~( m .bit ) -------- 15 or1 m.bit 6b 3 5 bit or c-flag : c ( c ) ( m .bit ) -------c 16 or1b m.bit 6b 3 5 bit or c-flag and not : c ( c ) ~( m .bit ) -------c 17 set1 dp.bit x1 2 4 set bit : ( m.bit ) ?1? -------- 18 seta1 a.bit 0b 2 2 set a bit : ( a.bit ) ?1? -------- 19 setc a0 1 2 set c-flag : c ?1? -------1 20 setg c0 1 2 set g-flag : g ?1? --1----- 21 stc m.bit eb 3 6 store c-flag : ( m .bit ) c -------- 22 tclr1 !abs 5c 3 6 test and clear bits with a : a - ( m ) , ( m ) ( m ) ~( a ) n-----z- 23 tset1 !abs 3c 3 6 test and set bits with a : a - ( m ) , ( m ) ( m ) ( a ) n-----z-
gms800 series mar. 2005 vii branch / jump operation no. mnemonic op code byte no cycle no operation flag nvgbhizc 1 bbc a.bit,rel y2 2 4/6 branch if bit clear : -------- 2 bbc dp.bit,rel y3 3 5/7 if ( bit ) = 0 , then pc ( pc ) + rel 3 bbs a.bit,rel x2 2 4/6 branch if bit set : -------- 4 bbs dp.bit,rel x3 3 5/7 if ( bit ) = 1 , then pc ( pc ) + rel 5bcc rel 50 2 2/4 branch if carry bit clear if ( c ) = 0 , then pc ( pc ) + rel -------- 6bcs rel d0 2 2/4 branch if carry bit set if ( c ) = 1 , then pc ( pc ) + rel -------- 7 beq rel f0 2 2/4 branch if equal if ( z ) = 1 , then pc ( pc ) + rel -------- 8bmi rel 90 2 2/4 branch if minus if ( n ) = 1 , then pc ( pc ) + rel -------- 9bne rel 70 2 2/4 branch if not equal if ( z ) = 0 , then pc ( pc ) + rel -------- 10 bpl rel 10 2 2/4 branch if minus if ( n ) = 0 , then pc ( pc ) + rel -------- 11 bra rel 2f 2 4 branch always pc ( pc ) + rel -------- 12 bvc rel 30 2 2/4 branch if overflow bit clear if (v) = 0 , then pc ( pc) + rel -------- 13 bvs rel b0 2 2/4 branch if overflow bit set if (v) = 1 , then pc ( pc ) + rel -------- 14 call !abs 3b 3 8 subroutine call 15 call [dp] 5f 2 8 m( sp) ( pc h ), sp sp - 1, m(sp) (pc l ), sp sp - 1, if !abs, pc abs ; if [dp], pc l ( dp ), pc h ( dp+1 ) . -------- 16 cbne dp,rel fd 3 5/7 compare and branch if not equal : -------- 17 cbne dp+x,rel 8d 3 6/8 if ( a ) ( m ) , then pc ( pc ) + rel. 18 dbne dp,rel ac 3 5/7 decrement and branch if not equal : -------- 19 dbne y,rel 7b 2 4/6 if ( m ) 0 , then pc ( pc ) + rel. 20 jmp !abs 1b 3 3 unconditional jump 21 jmp [!abs] 1f 3 5 pc jump address -------- 22 jmp [dp] 3f 2 4 23 pcall upage 4f 2 6 u-page call m(sp) ( pc h ), sp sp - 1, m(sp) ( pc l ), sp sp - 1, pc l ( upage ), pc h ?0ff h ? . -------- 24 tcall n na 1 8 table call : (sp) ( pc h ), sp sp - 1, m(sp) ( pc l ),sp sp - 1, pc l (table vector l), pc h (table vector h) --------
gms800 series viii mar. 2005 control operation & etc. no. mnemonic op code byte no cycle no operation flag nvgbhizc 1brk 0f 1 8 software interrupt : b ?1?, m(sp) (pc h ), sp sp-1, m(s) (pc l ), sp sp - 1, m(sp) (psw), sp sp -1, pc l ( 0ffde h ) , pc h ( 0ffdf h ) . ---1-0-- 2 di 60 1 3 disable all interrupts : i ?0? -----0-- 3 ei e0 1 3 enable all interrupt : i ?1? -----1-- 4 nop ff 1 2 no operation -------- 5pop a 0d 1 4 sp sp + 1, a m( sp ) 6pop x 2d 1 4 sp sp + 1, x m( sp ) -------- 7pop y 4d 1 4 sp sp + 1, y m( sp ) 8 pop psw 6d 1 4 sp sp + 1, psw m( sp ) restored 9push a 0e 1 4 m( sp ) a , sp sp - 1 10 push x 2e 1 4 m( sp ) x , sp sp - 1 -------- 11 push y 4e 1 4 m( sp ) y , sp sp - 1 12 push psw 6e 1 4 m( sp ) psw , sp sp - 1 13 ret 6f 1 5 return from subroutine sp sp +1, pc l m( sp ), sp sp +1, pc h m( sp ) -------- 14 reti 7f 1 6 return from interrupt sp sp +1, psw m( sp ), sp sp + 1, pc l m( sp ), sp sp + 1, pc h m( sp ) restored 15 stop ef 1 3 stop mode ( halt cpu, stop oscillator ) --------
b. mask order sheet mask order & verification sheet 1. customer information company name application order date yyyy tel: fax: name & signature: .otp file file name (please check mark into ) customer should write inside thick line box. 42sdip 44mqfp ( ) .otp customer?s logo package 8k 24k rom size (bytes) mask data check sum ( ) 2. device information mm dd a000 h (24k) c000 h (16k) ffff h 3. marking specification customer logo is not required. yyww korea mc80c02xx-mc customer?s part number if the customer logo must be used in the special mark, please subm it a clean original of the logo. 4. delivery schedule date quantity magnachip confirmation yyyy mm dd yyyy mm dd customer sample risk order pcs pcs e-mail address: 5. rom code verification yyyy mm dd verification date: please confirm out verification data. check sum: tel: fax: name & signature: e-mail address: yyyy mm dd approval date: i agree with your verific ation data and confirm you to make mask set. tel: fax: name & signature: e-mail address: 08 or 16 or 24 set ?00 h ? in blanked area yyww korea mc80c02xx-mc 3.0v 2.7v not use 2.4v * pfd option mc80c02 - mc 16k e000 h (8k)

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